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Evgeny Chernyavskiy
Design Technology Interface Expert(The company name is only visible to registered members)
- Biel
- Switzerland
Personal information
- Haves
- switching converter topologies, digital control systems, layout design, process flow, Simulation HSPICE, Unix design systems experience, RFIC, BiCMOS, CMOS technology, wafer processing technologies, process interaction, device yield, Systems on Chip, SoC, Dual Gate Oxide, DGO, ASIC design, clock/power distribution and analysis, RC extraction, timing analysis, full-custom IC layout, IC layout verification, DRC, EDA tools, MEMS design, Design and manufacturing MOS Gated Power Devices, Carrier Lifetime Measurements, CV Measurements, Chip reliability test, STI isolation, Trench refill, Chemical Mechanical Planarization process, Detectors Design and manufacturing, Humidity Sensor, Integrated Capacitor, Pressure Sensor, Bulk Silicon, ChemFET, BIB, Blocked Impurity Band, Photodetector, flip chip mounting, linear array, MOS controlled thyristor, MCT, simulation, design, manufacturing, Press Pack, IGBT, Solar Cell, multisilicon, wafer, efficiency, Avalanche Photodiode, 3D Single Event Upset, optimization, Semiconductor device model, VHDL, simulator, submicron, SOI, MOSFET, superjunction, CoolMOS
- Groups
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Professional experience (6 years, 1 month)
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Mar 2011
- present
(1 year, 3 months)
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(Only visible for registered members)
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Mar 2011
- present
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Aug 2010
- Feb 2011
(7 months)
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Inependent Semiconductor Professional
Self-Employed, http://semiweb.kilu.de
Industry: Semiconductors
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Aug 2010
- Feb 2011
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Nov 2009
- Jul 2010
(9 months)
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Industry: Electrical Engineering
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Nov 2009
- Jul 2010
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Dec 2005
- May 2009
(3 years, 6 months)
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Industry: Semiconductors
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Dec 2005
- May 2009
- Employment status
- Freelancer
Educational background
- Jan 2000 - Jan 2004
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Institute of Semiconductor Physics
Semiconductor Physics, Ph.D. in Semiconductor Physics and Solid State Electronics
- Languages
- English (First language), Russian (First language), German (Good knowledge)
About me
High experience with layout design and optimization, process flow.
Simulation experience with HSPICE, TCAD tools and environments, Unix design systems experience.
Design and develop RFICs in BiCMOS or sub-micron IC CMOS technology, identifying and analyzing performance requirements and implementing robust, manufacturable designs with best-in-class performance.
Good working knowledge of advanced CMOS and RF wafer processing technologies and process interactions that affect device yields, including Systems on Chip (SoC) with Dual Gate Oxide (DGO).
Experience in ASIC design, clock/power distribution and analysis, RC extraction, timing analysis.
Experience with full-custom IC layout
Experience in IC layout verification (DRC)
Skilled in use of EDA tools for MEMS/NEMS design and analysis.
Skilled in Design and manufacturing MOS Gated Power Devices.
Skilled in Carrier Lifetime Measurements, CV Measurements, Chip reliability test.
Skilled in STI isolation, Trench refill, Chemical Mechanical Planarization processes.
Implemented Projects:
· Detectors Design and manufacturing: Humidity Sensor (Integrated Capacitor), Pressure Sensor (Bulk Silicon orientation (110)
· ChemFET and enzyme - protein sensitive FET
· Design and manufacturing BIB (Blocked Impurity Band) Photodetector for the 12-16 micron wavelength, 64x64 array, flip chip mounting with multiplexor, cooled T=10 K.
· Design and manufacturing 64 cells microbolometer linear array.
· Simulation, design, manufacturing and testing MOS controlled thyristor (2500V, 50 A)
· Simulation, design, manufacturing and testing Press Pack HV-IGBT (4500V, 40 –1000A)
· Simulation, design and manufacturing Solar Cells made with multisilicon wafers, 9,5% efficiency
· Avalanche Photodiode simulation (3D Single Event Upset) and optimization
· Semiconductor device models implemented with VHDL simulator
· Simulation and design submicron SOI MOSFET
· Design and manufacture SJ MOSFET Devices (CoolMOS)
· Design and manufacture Junction Termination Extension Variation Lateral Doping (JTE VLD), own theoretical results in design optimization.
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Contacts
Rolf Neitzer, Edmond Niculin, Klaus Turski, Ralf Hartmann(More contacts may only be viewed by registered member)