Vishal Mahajan
Intern / Asic Design and Verification Engineer / Digital Hardware Designer / Tra
Delhi, Indien
Werdegang
Berufserfahrung von Vishal Mahajan
Intern / Asic Design and Verification Engineer / Digital Hardware Designer / Tra
---
Ausbildung von Vishal Mahajan
4 Jahre, Aug. 2008 - Juli 2012
Electronics and Communication Engineering
Punjab Technical University
Digital Design using Verilog Functional Verification using System Verilog VLSI design using VHDL Analog Design C, C++ OOD
Sprachen
Englisch
-