Ubaidullah Hussaini Syed
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Ubaidullah Hussaini Syed
- Bis heute 4 Jahre und 2 Monate, seit Apr. 2021
Pre Silicon Verification Engineer
Intel Microelectronics Sdn Bhd
- 7 Monate, Sep. 2020 - März 2021
Senior Post Silicon Validation Engineer
Intel Microelectronics Sdn Bhd
- 1 Jahr und 10 Monate, Aug. 2018 - Mai 2020
Technical Analyst [Engineering Lead]
UST Global Sdn Bhd
- 5 Monate, Okt. 2010 - Feb. 2011
IT Consultant
mediaconcepts
- 3 Jahre, Jan. 2007 - Dez. 2009
Senior Design Engineer
Toshiba Electronics Europe GmbH
High level Verification of MIPI specified peripheral modules using VERA and System Verilog. Activities include: -writing verification plans -writing simulation scripts in Csh and perl -setting up of constraint random, functional coverage driven and transaction modeling capable test bench environments -error injection and illegal behaviour analysis -writing reference models -communicating and mainitaining error reports -generating and analysing RTL coverage reports -documentation
- 5 Jahre und 2 Monate, Nov. 2001 - Dez. 2006
Design Engineer
Toshiba Electronics Europe GmbH
Design and verification of modules for Navigation/airbag-radio SoCs. Activities: -Design of Comp Window Watchdog Timer/Pulse Width Time Modulation Unit/Graphics Bus Bridge/RealTime Unit/Topl level Integration -Verification of Complex Graphics Engines using constrained random and TLM capable VERA TBs -Verification of Graphics Display Controller using simple directed testbenche using VERA -Chip level verification of various modules like DMA/CAN -Functional pattern extraction and STIL simulation
- 5 Monate, Mai 2001 - Sep. 2001
Graduate Engineer
Infineon Technologies AG
Study of Bluetooth protocols Testing of Bluetooth stack protocols for DECT devices. Verification of Serial Communication Interface.
- 6 Monate, Juni 2000 - Nov. 2000
Exchange Research Student
Oregon State University
1.Hardware implementation of On-line addition, multiplication and division algorithms 2.Design and Synthesis (ASIC/FPGA) of 16/32/64-bits On-line divider to study broadcasting delay problems 3.Employ Linear Sequential Array technique to design an On-line divider to overcome the broadcasting delay problem.
- 3 Monate, Jan. 1999 - März 1999
Lab Mentor
ASIC Design Center FH-Offenburg
Prepared students lab work manual. Assisted students in lab work. Designed Watchdog timer for FHOP-Processor
- 3 Monate, Jan. 1998 - März 1998
Trainee
Ministry of Defence Research Centre Imarat
contributed in the development of CPLD implementation of a multiport ethernet network repeater using VHDL.
Ausbildung von Ubaidullah Hussaini Syed
- 2 Jahre und 6 Monate, Okt. 1998 - März 2001
Communication and Media Engineering
University of Applied Sciences Offenburg
DSP, Digital Communication, VLSI, Interactive Distributed Applications, Database Management, Multimedia, Coding Techniques, Strategic Management, Rhetoric, International Purchasing
- 3 Jahre und 10 Monate, Sep. 1994 - Juni 1998
Electronics and Communication Engineering
Osmania University Hyderabad, India
Electronics Devices and Circuits, Logic Switching Theory, Network and Transmission lines, DSP, Computer Architecture, C, Electromagnetic Theory, Antenna and Radar theory, Digital Communication, Basic Circuit Analysis, Feedback Control Theory, Engg. Mathematics, Engg. Graphics,Fortran
Sprachen
Englisch
Fließend
Deutsch
Gut
Arabisch
Grundlagen
Urdu
-
Hindi
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