
Ubaidullah Hussaini Syed
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Ubaidullah Hussaini Syed
- Current 5 years and 2 months, since Apr 2021
Pre Silicon Verification Engineer
Intel Microelectronics Sdn Bhd
- 7 months, Sep 2020 - Mar 2021
Senior Post Silicon Validation Engineer
Intel Microelectronics Sdn Bhd
- 1 year and 10 months, Aug 2018 - May 2020
Technical Analyst [Engineering Lead]
UST Global Sdn Bhd
- 5 months, Oct 2010 - Feb 2011
IT Consultant
mediaconcepts
- 3 years, Jan 2007 - Dec 2009
Senior Design Engineer
Toshiba Electronics Europe GmbH
High level Verification of MIPI specified peripheral modules using VERA and System Verilog. Activities include: -writing verification plans -writing simulation scripts in Csh and perl -setting up of constraint random, functional coverage driven and transaction modeling capable test bench environments -error injection and illegal behaviour analysis -writing reference models -communicating and mainitaining error reports -generating and analysing RTL coverage reports -documentation
- 5 years and 2 months, Nov 2001 - Dec 2006
Design Engineer
Toshiba Electronics Europe GmbH
Design and verification of modules for Navigation/airbag-radio SoCs. Activities: -Design of Comp Window Watchdog Timer/Pulse Width Time Modulation Unit/Graphics Bus Bridge/RealTime Unit/Topl level Integration -Verification of Complex Graphics Engines using constrained random and TLM capable VERA TBs -Verification of Graphics Display Controller using simple directed testbenche using VERA -Chip level verification of various modules like DMA/CAN -Functional pattern extraction and STIL simulation
- 5 months, May 2001 - Sep 2001
Graduate Engineer
Infineon Technologies AG
Study of Bluetooth protocols Testing of Bluetooth stack protocols for DECT devices. Verification of Serial Communication Interface.
- 6 months, Jun 2000 - Nov 2000
Exchange Research Student
Oregon State University
1.Hardware implementation of On-line addition, multiplication and division algorithms 2.Design and Synthesis (ASIC/FPGA) of 16/32/64-bits On-line divider to study broadcasting delay problems 3.Employ Linear Sequential Array technique to design an On-line divider to overcome the broadcasting delay problem.
- 3 months, Jan 1999 - Mar 1999
Lab Mentor
ASIC Design Center FH-Offenburg
Prepared students lab work manual. Assisted students in lab work. Designed Watchdog timer for FHOP-Processor
- 3 months, Jan 1998 - Mar 1998
Trainee
Ministry of Defence Research Centre Imarat
contributed in the development of CPLD implementation of a multiport ethernet network repeater using VHDL.
Ausbildung von Ubaidullah Hussaini Syed
- 2 years and 6 months, Oct 1998 - Mar 2001
Communication and Media Engineering
University of Applied Sciences Offenburg
DSP, Digital Communication, VLSI, Interactive Distributed Applications, Database Management, Multimedia, Coding Techniques, Strategic Management, Rhetoric, International Purchasing
- 3 years and 10 months, Sep 1994 - Jun 1998
Electronics and Communication Engineering
Osmania University Hyderabad, India
Electronics Devices and Circuits, Logic Switching Theory, Network and Transmission lines, DSP, Computer Architecture, C, Electromagnetic Theory, Antenna and Radar theory, Digital Communication, Basic Circuit Analysis, Feedback Control Theory, Engg. Mathematics, Engg. Graphics,Fortran
Sprachen
English
C1 (Fließend)
German
B1-B2 (Gute Kenntnisse)
Arabic
A1-A2 (Grundkenntnisse)
Urdu
Hindi
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