Aleksei Khailov

Angestellt, Design verification engineer, OhT

Edinburgh, Vereinigtes Königreich

Über mich

Cutting-edge technology is my passion. After more than 15 years of experience in FPGA and ASIC design and verification I am still curious about everything that is new in the industry. I need help with the relocation from an autocratic country.

Fähigkeiten und Kenntnisse

SystemVerilog
UVM
Verification and validation
SVA
Functional Coverage
VIP
System on Chip (SOC)
ASIC
Verilog
Engineering
VHDL
FPGA

Werdegang

Berufserfahrung von Aleksei Khailov

  • Bis heute 18 Jahre, seit Juni 2006

    Design verification engineer

    OhT

Sprachen

  • Englisch

    Gut

Interessen

Snowboarding

XING Mitglieder mit ähnlichen Profilangaben

Frank Teske-Schmeling

Technischer Sachbearbeiter

Braunschweig

Chao Chieh Hsu

Senior Verification IP Engineer, Project Lead

Taipei

Johannes Walter

FPGA Engineer

San Francisco

Bhavik Markana

Si FE CAD Engineer

Bengaluru

Mehran Goli

Researcher

Bremen

Ganesh Vairavan

Design-Verifikations-Ingenieur

Chennai, State of Tamil Nādu, India

Khaled Ismail

HDL Embedded Systems Engineer

Darmstadt, Hesse, Germany

TW Huang

Principal Digital Verification Engineer

Hsinchu

Mohamed DBARA

Verification engineer

Ariana

Sergey Dubinin

Staff Digital Design and Verification Engineer | CSS dpt.

Austria

Avdhesh Sharma

Wissenschaftlicher Mitarbeiter

Netphen

Ponnu Priya P V

Senior Validation Engineer

Bangalore

Jason Sprott

CTO | Consultant | Co-Founder

Edinburgh

Mariano Mate

Senior Technical Consultant

Madrid

WALID BOUKRA

FPGA and ASIC design engineer

Paris

Anudeep Teegala

---

Hyderabad

Mahmud Rezwan Hussain

Senior Verification Engineer

Eindhoven

Norman Seßler

Senior Digital Verification Engineer

Dresden

Saurabh Singh

Systems Engineer

Munich

Mohammed Abdelmonem

Senior VLSI Design and verification engineer

Cairo

21 Mio. XING Mitglieder, von A bis Z

Nachname:

ABCDEFGHIJKLMNOP
QRSTUVWXYZ