Kaushik Jayaraja Reddy

"Development of an FPGA design for the evaluation of high performance PCI express DMA(Direct Memory Access) controller core for a new software platform" IP Cores and FPGA Device - Stratix V DSP Development kit, Altera's StratixV PCI Express Hard IP Core, Rohde & Schwarz's DMA controller core. Interfacing the the DMA with DDR3 SDRAM for throughput evaluation. Tools used - Quartus Prime 15.1, Modelsim HDL Designer, Aldec Riviera Pro, Lecroy PETracer(PCIe bus analyser) Programming Language – VHDL.

Adaptation of a VHDL based MJPEG2000 decoder for high resolution video frames. Development of Matlab scripts for chroma resampling and DCT computation for design verification. DCT/IDCT core implementation for the CODEC . Functional simulation and analysis of the sub blocks and the complete system.

Development and maintenance of firmware for Bosch Automotive diagnostic devices. Developing the software using Embedded C programming. Developing ECU simulators using Bus analyser tool HS-X from Samtec. Fixing issues reported by Coverity static code analysis tool. Familiar with OBD II protocols like ISO 15765(CAN based) ,ISO9141/ISO14230(KWP2000), SAE J1850. Developing CppUnit tests for various ECUs.

Object oriented programming ,Advanced Programming Techniques, Technical project management ,Advanced Embedded Operating Systems, Complex digital architecture , signal processing hardware , CMOS analog circuit design ,Microelectronic System Design and Testing ,Vhdl Programming.