Dr. Matthias Gries
Bis 2024, Principal Engineer - CPU, SoC, memory architecture R&D, Huawei Technologies
München, Deutschland
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Berufserfahrung von Matthias Gries
9 Jahre, Juni 2015 - Mai 2024
Principal Engineer - CPU, SoC, memory architecture R&D
Huawei TechnologiesMunich Research Center (MRC) -- Advanced Computing R&D: Application-driven codesign of memory, compute and interconnect for Arm AArch64 platform SoCs (System-on-Chip) with focus on servers, data centers and scientific computing/HPC software enabling.
4 Monate, Feb. 2015 - Mai 2015
Senior Systems Engineer
Roche Diagnostics GmbH
7 Jahre und 9 Monate, Apr. 2007 - Dez. 2014
Senior Research Scientist - memory hierarchy, manycore SoC integration
Intel GmbH
technical lead: Design methods, hardware & software technologies for memory subsystems and energy efficient multicore platforms. - Non-Volatile Memory (PCM, STT) integration into memory & storage hierarchy - Manycore CPU SCC (Single-chip Cloud Computer) DDR3 subsystem design - Predictive methods for application-driven resource management (thermal & power control [DVFS])
2 Jahre und 9 Monate, Juli 2004 - März 2007
System Engineer / Researcher - network processing
Infineon TechnologiesImplemented thin system SW layer (C/C++) w/ min. mem footprint for proprietary network processor, prototyped bus control on FPGA for MP-SoC (OCP on-chip communication, ethernet, IPv4 forwarding), concept engineering of DSLAM network processor & WLAN IEEE 802.11n access point processor (AMBA, OCP, CoreConnect, PCIe, MIPS core IP, IEEE 802.3).
2 Jahre und 2 Monate, Mai 2002 - Juni 2004
Post-doctoral researcher
UC Berkeley
Developed automation tools for designing application-specific instruction-set processors, evaluated architectures and programming models for network processors.
Teaching assistant for classes on hardware-software codesign, computer architecture, computer networks, operating systems, and embedded systems' design.
Ausbildung von Matthias Gries
4 Jahre und 6 Monate, Feb. 1997 - Juli 2001
Computer Engineering
ETH Zürich
network processing, Quality of Service, active queue management, real-time scheduling
5 Jahre und 4 Monate, Okt. 1991 - Jan. 1997
Electrical Engineering / Nachrichtentechnik
TU Hamburg-Harburg
digital signal processing, image processing, computer architecture, filter design
Sprachen
Deutsch
Muttersprache
Englisch
Fließend