Mag. Mina Benyamine

o Project layout lead for several industrial & COMs on Finfet, 28nm, 40nm,180nm technology nodes.  Leading a team of several layout engineers, resource assigning, time planning, layout guidelines alignment, and conducting layout reviews. o Chip layout lead for several Industrial ethernet, I/O & High-Speed Industrial I-coupler ICs.  Chip level floor planning, layout & integration & bonding diagrams.  Layout lead for 2 GHz Clock generation PLL sub-system. o Layout of several blocks of 28nm LMR IC ADC.

 Design and layout of Temperature sensor, bandgap, clock generator, reference current circuit, high speed receiver decoder.  Layout of High voltage pulser, LNA, output buffer and other chip sub-blocks.  Chip floor-planning and top-level integration and verification.

Chip layout lead for wireless charging ICs. New layout for blocks in the PLL hierarchy and Mixers with other strategic layout changes for macros and chip level. Full Chip verification and tape out procedure. Chip layout lead for integrated micro-spectrometer. Strategic layout changes for High voltage macros, ESD cells and Pad frame. Chip level integration, verification and tape out procedure. ASIC bio-implant nerves stimulating Chip. Chip and sub modules floorplan. Layout for DC-DC macro and LDOs.

Worked on several WiFi/Bluetooth transceivers tapouts. Layout lead for 5Ghz & 10Ghz VCO, plus LO distribution and PLL hierarchy. Responsible for new layout hierarchies, as well as strategic revision changes for macros and sub blocks levels at 65/55/40 nm technology nodes as (PMU cells – DC-DC Voltage converters – Bandgap – LDOs – DACs – ADCs – Dividers – Filters – Comparators – LNAs – Mixers - RTC). Travel between USA and Egypt to gain a solid team communication and experience.

Worked on several cellular transceivers tapouts. Responsible for layout of RF and Power management sub blocks at different technology nodes (Bandgap – LDOs – DACs – ADCs – Dividers – Filters – Comparators – PLLs – LNAs – Oscillators).

Master thesis “An on-chip 32 stage interleaved switched capacitor DC-DC converter design.” Courses included Analog IC design, Full custom IC design, High performance ICs, ASIC & FPGA, CAD, System Engineering, Project Management and Software requirements.

Graduation Project: Touch screen micro-controlled car with object detection and avoidance system