SYED FARAZ UDDIN

is researching.

Bis 2021, SENIOR PCB DESIGNER, R&D ALTANOVA

Abschluss: BACHELORS OF (ELECTRONIC ENGINEERING), Sir Syed University of Engineering and Technology

Bietigheim-Bissingen, Deutschland

Fähigkeiten und Kenntnisse

HDI PCB
PCB design systems
OrCAD
cadence allegro
IC package designing
substrate designing
Schematic designing
Gerber format
CAM350
gerber checking
Cadence allegro package designer
Multi-Chip-Modul
MS Excel
MS Word
MS PowerPoint
pcb designer
Engineering
Semiconductor
KiCad

Werdegang

Berufserfahrung von SYED FARAZ UDDIN

  • 1 Jahr und 10 Monate, Juni 2021 - März 2023

    PCB designer

    iPronics Programmable Photonics

  • 1 Jahr und 10 Monate, Juni 2021 - März 2023

    PCB layout engineer

    iPronics

  • 5 Jahre und 4 Monate, Feb. 2016 - Mai 2021

    SENIOR PCB DESIGNER

    R&D ALTANOVA

    Highly focused and analytical engineering professional with a strong technical background in IC package designing & Semiconductor testing industry.Currently working in a US styled environment. Committed to achieving all goals in a highly efficient manner while meeting deadlines. • Design multilayered and HDI testing PCB's using industry standard techniques. • Responsible for completing ATE PCB designs using CADENCE ALLEGRO, ORCAD. • Designing Substrate design PCB’s on (Allegro Package Designer)

Ausbildung von SYED FARAZ UDDIN

  • 4 Jahre und 3 Monate, Jan. 2011 - März 2015

    Electronics and Communication Engineering

    Sir Syed University of Engineering and Technology

Sprachen

  • Englisch

    Fließend

  • Deutsch

    Grundlagen

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