Shyam Gaurav Ramesh

Designed analog and mixed signal sub blocks for ADCs in RF applications Assisted the team in behavioural modelling of analog blocks in order to facilitate verification process Created layouts for designed blocks and also provided extensive layout support for senior engineers in 28nm CMOS tech. Responsible for technical documentation that would assist in verification and evaluation phase

Title: "Bandwidth Enhancement using Cross-Coupled Pairs in Multi-Gigabit Wireline Tramsmitters for Automotive Application" Analysis of Cross-Coupled Pair as a negative capacitor Stability and bandwidth analysis of Cross-Coupled Pair when connected in conjunction with CML tapered buffer chain Theoretical modelling of the Cross-Coupled Pair to provide an efficient design methodology Simulation and verification of circuit with the model Implemented the design and layout in 55nm CMOS tech,

Designed CML driver and tapered buffer chain (pre-drivers) with pre-emphasis used in high speed wireline transmitters Performed S-Parameter simulations to verify impedance matching of the driver Handled corner and post-layout simulations to create a robust design

Project : Micromachined (MEMS based) Piezoresistive Pressure Sensor. Performed stress analysis of sensor for various temperature and pressure variations Calibrated the sensor using Sensor Signal Conditioner IC to compensate offset & temperature drift Created mask layouts that were used to fabricate MEMS Sensor

IC Design – Transistor level, Micro and Nano Devices, Semiconductor physics / Nano structures, Microsystem design, Technologies for micro and nano systems, Advanced integrated circuit technology, System Design

Analog Electronic Circuits, Fundamentals of CMOS VLSI, Analog and Mixed Mode VLSI design, Fundamentals of HDL & Digital System Design using VHDL