Ganesh Pagadala
Angestellt, CAD/EDA Tools Engineer & Analog Layout Engineer, Intel Corp.
Penang, Malaysia
Über mich
Skilled and experienced CAD/EDA tools engineer & Analog Layout Engineer with 7+ years of experience in analog ,mixed signal and RF designs across various technology nodes including 180nm, 90nm, 45nm,28nm,16nm,10nm,7nm, 5nm & N3 under different foundry's like INTEL, TSMC, SANDISK and GF . Technical Skills Expertise: 1. Technologies: Cadence virtuoso(layout-EXL & schematic- XL), ADE spectre & Fusion Compiler 2. Programming Skills: SKILL, Perl, C-Shell & Python 3. Operating System: Unix & Windows 4. Verification Checks: Antenna, Density, ESD, PERC, LV, HV, RV and IP handoff. 5. Verification Tools: Calibre, Hercules, ICV, Assura & PVS. 6. Timing: Siliconsmart & Primetime. 7. Extraction & Reliability Tools: star RC, Totem, Quantus and voltus-FI.
Werdegang
Berufserfahrung von Ganesh Pagadala
Bis heute 4 Jahre und 4 Monate, seit Feb. 2020
CAD/EDA Tools Engineer & Analog Layout Engineer
Intel Corp.o Experienced in HDK validation of INTEL & TSMC process which includes TFM, cell library and PDK to improve design efficiency and IP handoff. o Estimated PPA on various technology nodes using analog designs. o Evaluated analog layout TFM functionality for different process, participated in full-chip integration and develop automation scripts in SKILL. o Lead performance bench marking of analog & digital flows and work with internal/external EDA vendors to deploy solutions in project environment.
Bis heute 6 Jahre und 1 Monat, seit Mai 2018
Analog Layout Engineer
UST Global, Malaysia
Product Development Engineer, Client Location at Intel and Cypress Semiconductor. o Experience indifferent generations of FinFET included 10nm and22nm. o Expertise in handling TAPE-OUT closure activities in the chip level integration. o Provided Analog Layout Training for fresh graduates who joined the team. o Awarded as EXECUTION MINDSET(Client Comforter) from country head.
3 Jahre und 4 Monate, Jan. 2015 - Apr. 2018
Mask Design Engineer
Western Digital Corporation
o Experienced in 2D(NAND),3D-Memory(BiCS) sub blocks layout design Including like Charge Pumps (VMSYS),Digital Temperature Co-efficient (DTCO) , Word Line Leakage Detection (WLLD), YLOG(SERDES),Voltage Generators (VOLGEN), Power Amplifier(PWON),Clock Generator (CLKGEN),IO Pads and ESD’s. o Effectively involved in the Standard cells & Macro cells library development of various generations. o Mentored Resources as a BLOCK LEAD and Explored different process Automation Techniques and addressed the team.
6 Monate, Aug. 2014 - Jan. 2015
Trainee Graduate
Mos Chip Institute of silicon Systems
o Focused on sub micron technology nodes like1 30nm, 90nm, 45nm, 28nm and process included TSMC,GF. o Designed layouts for Digital/Analog/Mixed/RF sub blocks including Standard Cells,Level Shifter,OP-AMP,BGR,DAC and PLL. o Acquired knowledge on PCELL creation and Analog/RF Layout Techniques like Matching,Shielding, parasitic optimization and Noise Isolation.
Ausbildung von Ganesh Pagadala
3 Jahre und 9 Monate, Okt. 2010 - Juni 2014
Electronics and Communication Engineering
Jawaharlal Nehru Technological University, Anantapur
Main Emphasis – V L S I , Analog and Digital Electronics,circuit thoery,Antennas, Microwave,signals and systems,Control Systems,Communications.
Sprachen
Englisch
Fließend