Joel Viray
Angestellt, Senior Engineer TD Device Engineering, GLOBALFOUNDRIES
Singapore, Singapur
Werdegang
Berufserfahrung von Joel Viray
Bis heute 11 Jahre und 11 Monate, seit Aug. 2012
Senior Engineer TD Device Engineering
GLOBALFOUNDRIES• Develop and implement robust electrostatic discharge (ESD) and electrical overstress (EOS) protection design rules, guidelines and methodologies, and include mitigation of latch-up effects. • Work closely with several internal groups such as various users in different fabs, design enablement group, device owners, spice model development teams, etc., to ensure proper implementation of ESD to meet corporate and customer needs and goals.
1 Jahr und 2 Monate, Juli 2011 - Aug. 2012
Senior Layout Design Engineer
Altera Corporation (M) Sdn Bhd
• Work for pad ring and power management for Altera devices and its proliferations and work closely with ICD and Package team to ensure the quality delivery is meeting design intent
4 Jahre und 11 Monate, Juli 2006 - Mai 2011
Design Engineer I
Sanyo Semiconductor Manufacturing Philippines - Philippine Design Center
• Responsible on Custom IC layout in Bipolar, CMOS and BiCMOS technologies from circuit schematics using Cadence Virtuoso layout toolset and JEDAT EDA tools.
Ausbildung von Joel Viray
5 Jahre und 5 Monate, Juni 2000 - Okt. 2005
Bachelor of Science in Electronics and Communications Engineering
Saint Louis University, Baguio City
Sprachen
Englisch
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Japanisch
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Tagalog
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Ilocano
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