Santhosh Injineri
Praktikum, SystemC modeling / Verification Engineer, Cadence
Munich, Deutschland
Werdegang
Berufserfahrung von Santhosh Injineri
Bis heute 12 Jahre und 2 Monate, seit Apr. 2012
SystemC modeling / Verification Engineer
Cadence
Developed Loosely-timed TLM model of Denali memory controller, writing testbench (SystemC), bug fixing. Developed seamless, self checking verification environment written in e-Specman, UVM (Universal Verification Methodology), verify wide range of Denali DDR memory controllers, and perform timing analysis. Involved in verification planning (eplanner), regression testing (emanager), coverage analysis (IMC - incisive metric center), report generation. AXI3 protocol compliance checking.
1 Jahr und 9 Monate, Juni 2008 - Feb. 2010
Memeber of Technical Staff
SUN Microsystems
Implementation of Cloud API's for Storage offerings for SUN Cloud (Storage as Cloud). Handled QE team - Work Assignment, Status Report update.
1 Jahr und 11 Monate, Aug. 2006 - Juni 2008
Software Engineer
Hewlett Packard
Investigator, Designer, Developer, Tester, document Author and Support Engineer for MetroCluster EVA in the HP Clustering Environment ServiceGuard (SG), with Operating Environment version of HP-UX 11iv2 and 11i v3. Significant Partner contact, investigator and facilitator for integration on behalf of ECMT (Enterprise Cluster Master toolkit) for HP clustering product SG on HP-UX and Linux, SG Manager (SG GUI Project).
Ausbildung von Santhosh Injineri
Bis heute 14 Jahre und 3 Monate, seit März 2010
Embedded Computing Systems
University of Kaiserslautern
Architecture of Digital Systems, Synthesis and Optimization of Microelectronics, Verification of Digital Systems, Real-Time Systems, and Model Based Automotive Development.
3 Jahre und 9 Monate, Juni 2002 - Feb. 2006
Electronics and Communication
Visvevaraiah Technological University
Microprocessor 8085,8086, Motorola Digital and Analog Communication Logic Design VLSI
Sprachen
Englisch
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