PMU Mixed-Signal Design Verification Engineer - Early Career (m/f/d)
Munich , Bavaria-Bayern , Germany
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At Apple, we don’t just build great products — we revolutionize industries. It’s the diversity of our people and their ideas that drive the innovation to fuel everything we do, from amazing technology to industry-leading environmental efforts. Join Apple and be a part of our success.
The Silicon Engineering Group is responsible for developing cutting edge chips that can be found in all of your favourite Apple products. Our power management design team in Munich has a unique opportunity for a forward-thinking and creative Mixed-Signal Design Verification Engineer.
In this role, you will have the opportunity to experience a PMU from several levels of abstractions. Whether your passion is in the intricate details of how a sub-block within the PMU works, or the high level abstraction of system level use-cases and emulations, you will find your passion in your day-to-day business. You will be working closely with cross-functional teams to design and execute verification plans to meet specification requirements and project schedule.
Description
You will closely collaborate and engage with members of cross-functional disciplines including design teams, digital verification, system engineers and architects, and DfT teams to define and execute the verification strategy and test plan to cover a specified feature or IP.
Your tasks would include:
- Development of test plans covering the specified feature set and related checks and assertions
- Design verification from interactive test case debugging to automated regression
- Analysing verification results and debugging the design
- Planning and reviewing the verification results with cross-functional stakeholders
- Collaborating with design and DV teams targeting optimum verification coverage
- Develop behavioral models with different abstraction levels for analog IPs based on required verification targets
- Verification automation
- Experience in analog and mixed-signal verification and behavioral modeling
- Understanding of analog schematics and digital RTL
- Understanding of behavioral modeling and model validation techniques
- Knowledge of Verilog-AMS, Verilog, and System-Verilog
- Understanding of Assertion Based Verification
- Knowledge of verification automation concepts and scripting languages: TCL, Python/Perl is an advantage
- Knowledge of UVM (Universal Verification Methodology) is a plus
- Proactive team player with excellent communication skills able to collaborate with diverse cross-functional teams
- Fluency in English is required
BS/MS/PhD in Electrical Engineering or industrial experience equivalent
Early Career professionals with outstanding academic results and relevant internship experiences will also be considered
Additional Requirements
- Apple is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities.
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