Extending our international team, we are looking for a SoC Physical Design Engineer (Entry-Level).

Job Description:

• Become an expert in physical design of complex digital and mixed signal SoCs
• Work with EDA tools and our design flows to implement customer designs in leading edge technology nodes
• Support individual steps in RTL2GDS flow like Synthesis, P&R, Physical Verification, EMIR, LEC, STA
• Address challenges in designing SoCs in leading edge Technologies
• Contribute to methodology developments with proposals and implementation of flow and methodology enhancements

Requirements:

• Master’s Degree in Electrical Engineering or Information Technology or similar
• Basic knowledge of the RTL2GDS design flow
• Basic knowledge in hardware description languages
• Basic knowledge in TCL and Python programming
• Self-driven and hands-on way of working
• Strong analytical and solution-oriented thinking
• Very good written and oral communication skills in English
• Team-player

A plus would be:

• Experience with Digital-IC-EDA tools from Cadence, Synopsys and Siemens
• Experience in RTL2GDS in leading edge CMOS and/or FDSOI technologies
• Knowledge in timing modelling and timing analysis for digital designs
• Good written and oral communication skills in German