Your Role

As a Formal Verification Engineer at LUBIS EDA, you will have a dual responsibility:

1. Consulting Services :
2. Work directly with clients to verify their RTL designs and IPs.
3. Create, implement, and debug Assertion IP (AIP) based on customer verification requirements.
4. Develop properties , identify and report bugs, and collaborate with the client’s design team to resolve issues.
5. Ensure all verification deliverables meet quality standards and project timelines.
6. Software Automation :
7. Contribute to the design and development of LUBIS EDA’s in-house software tools for automating the Formal Verification process.
8. Collaborate with the software development team to develop new methodologies, enhance usability, and address customer pain points.
9. Project and Client Management (Senior/Staff Engineers):
10. Project Management :
11. Take ownership of formal verification projects, ensuring they are delivered on time, within scope, and to the highest quality.

• Plan project execution strategies, allocate resources, and track progress using project management tools.
• Lead technical reviews and provide mentoring to junior team members.

• Client Management :
• Serve as the primary technical point of contact for clients, ensuring their requirements are understood and met.
• Proactively manage client expectations, providing regular updates and addressing any concerns.
• Identify opportunities for additional client engagements or improvements to the verification process.
• Represent LUBIS EDA in client meetings, fostering trust and long-term relationships.

Key Responsibilities

• Analyze RTL designs, create properties, and run verification scenarios using formal tools (e.g., JasperGold , Questa Formal, Cadence IFV).
• Debug and analyze verification failures, working closely with the client’s design and verification teams.
• Automate repetitive tasks in verification workflows and contribute to toolchain improvements.
• Provide feedback from client projects to drive the roadmap for LUBIS EDA’s software solutions.
• Stay up-to-date with the latest advancements in formal verification tools, techniques, and industry trends.
• Document processes and methodologies to ensure knowledge sharing across the team.

Must-Have Skills :

• Solid understanding of Formal Verification techniques and tools.
• Experience in verifying complex RTL designs using formal methods.
• Proficiency in SystemVerilog Assertions (SVA) and usage of Formal Engines ( e.g. VCF) in the context of Formal Property Checking .

• Strong problem-solving and debugging skills.

Additional Skills for Senior/Staff Engineers :

• Proven experience in project and client management within the semiconductor or EDA industry.
• Strong leadership and mentoring skills.
• Ability to balance multiple projects and prioritize client needs.
• Experience in stakeholder communication and managing cross-functional teams