Research Project

Future generation automotive receivers for eg. FMCW MIMO radar reception require increasing larger bandwidths, higher dynamic range and spectral purity at low-power consumption. Conventional CT ADC architectures, such as continuous-time sigma-delta (SD), pipeline (CTP) and MASH sigma-delta modulators, face significant challenges in simultaneously achieving high DR, wide BW, and power efficiency. This project proposes the design and implementation of a time-interleaved continuous-time delta-sigma modulator (TI CT DSM) that leverages recent architectural innovations to overcome these limitations.

Objectives

Design of a time-interleaved CT DSM capable of multi-GS/s sampling rates and >400 MHz signal bandwidth with superior dynamic range, signal-to-noise-and-distortion ratio (SNDR), and power efficiency compared to state-of-the-art CTP and MASH ADCs.

Project Plan

• Phase 1: System architecture and behavioral modeling, define system specifications and performance targets

• Phase 2: Circuit design and simulation

• Phase 3: Layout, fabrication, and testing of prototype design

• Phase 4: Publication and benchmarking measured results with state-of-the-art CTP and MASH ADCs

Requirements for this role

• Master’s degree in electrical engineering or related field

• Strong background in analog/mixed-signal circuit design

• Background in data converters

• Experience in Cadence and Matlab

• 80 %-time commitment within a 3-year period, as this position is part time (80%) limited to 3 years

Interested in joining our team?

You will be working alongside NXP’s data converters team in Hamburg. The scientific work is done in cooperation with the University of Ulm, the institute of Microelectronics.

Submit your CV and personal background and let us talk about it!

Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary.