Dr. Alexander Fell

Angestellt, Leading Researcher, Barcelona Supercomputing Center

Abschluss: PhD, Indian Institute of Science

Barcelona, Spain


Embedded Systems
Hardware Design
Verilog Vhdl
System on Chip
Software Development


Professional experience for Alexander Fell

  • Current 3 years and 4 months, since Jul 2020

    Leading Researcher

    Barcelona Supercomputing Center

    The MareNostrum Experimental Exascale Platform (MEEP, https://meep-project.eu/) is a flexible FPGA-based emulation platform that will explore hardware/software co-designs for Exascale Supercomputers and other hardware targets, based on European-developed IP.

  • Current 4 years and 10 months, since Jan 2019

    Adjunct Professor

    Indraprashta Institute of Information Technology Delhi

  • 1 year and 4 months, Mar 2019 - Jun 2020

    Assistent Professor

    Singapore Institute of Technology

  • 1 year and 9 months, Jul 2017 - Mar 2019

    Cyber Security Research Scientist

    Nanyang Technological University

    In this work, I concentrate on two attacking scenarios: 1. Time Side Channel Attacks: An attacker correlates the execution time of a binary program executing on a low-noise embedded system on bare metal to extract internal implementation details of the victim program and even extract secret information such as cryptographic keys. 2. Reverse Engineer Attacks: In addition to further hide implementation details of the, the original source code is obfuscated making it unintelligible to an attacker.

  • 5 years and 6 months, Jul 2013 - Dec 2018

    Assistant Professor

    Indraprashta Institute of Information Technology Delhi

    Teaching Areas: Embedded Logic Design (BTech, 2nd year) Advanced Embedded Logic Design (MTech, 1st year, BTech elective) Introduction to Engineering Design (BTech, 1st year) Refresher Course in FPGA for BTech and MTech students Research Interests: Coarse Grain Reconfigurable Architectures (CGRAs), Network-on-Chip, Low Power Embedded Systems and Compilers

  • 7 months, Dec 2012 - Jun 2013

    Senior Researcher

    RWTH Aachen University

    Mapping of graphs is known to be an NP-complete problem. In Coarse Grained Reconfigurable Architectures (CGRA) this problem occurs, if a Data Flow Graph (DFG) needs to be mapped onto the available physical hardware. The mapping should not only achieve a high utilization of resources, but also avoid increasing the height of the graph (=execution time) of the application.

Educational background for Alexander Fell

  • 3 years and 11 months, Jan 2009 - Nov 2012

    Hardware Engineering, Multi-core Processor Architectures

    Indian Institute of Science

    Research topic: Exploration of reconfigurable data flow multi-core processors, SystemC REDEFINE simulator, Daedalus on REDEFINE, RECONNECT: A flexible Router Architecture for Network-on-Chips, Hardware simulation acceleration by using REDEFINE

  • 2005 - 2007

    FH Köln

    Graduation project at the Indian Institute of Science (IISc), Bangalore, India (February 2007 to August 2007) supported by DAAD scholarship; Topic: “Network on Chip Routers in a Dual Honeycomb Network”

  • 2001 - 2005

    FH Aachen

    Exchange semester at the Ferris State University, Big Rapids, Michigan, USA


  • English


  • German

    First language


Hardware Design
Embedded Systems
Internet of Things
IT Security



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