Dr. Alexander Fell

The MareNostrum Experimental Exascale Platform (MEEP, https://meep-project.eu/) is a flexible FPGA-based emulation platform that will explore hardware/software co-designs for Exascale Supercomputers and other hardware targets, based on European-developed IP.

In this work, I concentrate on two attacking scenarios: 1. Time Side Channel Attacks: An attacker correlates the execution time of a binary program executing on a low-noise embedded system on bare metal to extract internal implementation details of the victim program and even extract secret information such as cryptographic keys. 2. Reverse Engineer Attacks: In addition to further hide implementation details of the, the original source code is obfuscated making it unintelligible to an attacker.

Teaching Areas: Embedded Logic Design (BTech, 2nd year) Advanced Embedded Logic Design (MTech, 1st year, BTech elective) Introduction to Engineering Design (BTech, 1st year) Refresher Course in FPGA for BTech and MTech students Research Interests: Coarse Grain Reconfigurable Architectures (CGRAs), Network-on-Chip, Low Power Embedded Systems and Compilers

Mapping of graphs is known to be an NP-complete problem. In Coarse Grained Reconfigurable Architectures (CGRA) this problem occurs, if a Data Flow Graph (DFG) needs to be mapped onto the available physical hardware. The mapping should not only achieve a high utilization of resources, but also avoid increasing the height of the graph (=execution time) of the application.

Research topic: Exploration of reconfigurable data flow multi-core processors, SystemC REDEFINE simulator, Daedalus on REDEFINE, RECONNECT: A flexible Router Architecture for Network-on-Chips, Hardware simulation acceleration by using REDEFINE

Graduation project at the Indian Institute of Science (IISc), Bangalore, India (February 2007 to August 2007) supported by DAAD scholarship; Topic: “Network on Chip Routers in a Dual Honeycomb Network”

Exchange semester at the Ferris State University, Big Rapids, Michigan, USA