Dr. Alexander Fell

• Led and guided a team on the DARPA-funded UpDown Project • Designed, implemented, and improved the simulator for the UpDown system architecture from simulating 2048 compute cores and 10 MIPS to 32M compute cores executing 500 BIPS • Developed a high-performance compiler for the UpDown architecture, enabling algorithm experts to implement solutions in a high-level language • Collaborated with cross-functional teams to optimize parallel execution for real-world graph analyses

• Led the development of the memory processor for RISC-V cores within the Coyote simulator platform for MEEP, a self-hosted, disaggregated Accelerator for High-Performance Computing (HPC) • Explored advanced compiler optimizations in LLVM, focusing on machine instruction scheduling and variable provenance for RISC-V VPUs • Contributed to the design of hardware/software co-designs for Exascale Supercomputers

• Researched multi-objective optimization of program obfuscation, enhancing security measures • Reviewed scholarly articles for the Microelectronics Journal, contributing to the advancement of the field • Delivered engaging lectures to undergraduate students on computer organization, network systems, and mobile security, fostering a robust learning environment

• Conducted extensive research to mitigate Time Side Channel and Reverse Engineering attacks on embedded RISC-V systems using LLVM compiler support • Developed innovative strategies in LLVM to enhance security measures against potential vulnerabilities • Collaborated with interdisciplinary teams at Nanyang Technological University to advance the field of cybersecurity • Published impactful findings with Ben-Gurion University, Israel, improving system resilience against attacks

• Delivered engaging lectures in Embedded Logic Design and Advanced Embedded Logic Design to B.Tech. and M.Tech. students • Developed a comprehensive curriculum for Introduction to Engineering Design, emphasizing project execution in embedded systems • Conducted a refresher course in FPGA, enhancing students' practical skills and knowledge in low-power embedded systems • Collaborated with the Wildlife Institute of India to develop embedded systems for harsh Antarctic environments

• Conducted in-depth research on mapping graphs within Coarse-Grained Reconfigurable Architectures (CGRA) to optimize resource utilization • Developed a Force Directed Schedule and Mapping Algorithm to enhance execution time and efficiency • Collaborated with cross-functional teams at RWTH Aachen University, contributing to innovative solutions in hardware mapping

• Conducted in-depth research on reconfigurable data flow multi-core processors, specifically Coarse-Grained Reconfigurable Architectures (CGRA) • Developed and utilized the SystemC REDEFINE simulator for hardware simulation acceleration • Designed the RECONNECT architecture for Network-on-Chips, contributing to innovative routing solutions in a two-dimensional, minimal degree network.

• Graduation project at the Indian Institute of Science (IISc), Bangalore, India (February 2007 to August 2007) supported by DAAD scholarship; Topic: “Network on Chip Routers in a Dual Honeycomb Network”

• Exchange semester at Ferris State University, Big Rapids, Michigan, USA • Thesis completed at The Institute of Mathematical Sciences (IMSc), Chennai, India; Title: "A feasibility Study to improve Results of Search Engines" • Speaker to encourage students to study abroad