Alexander Ruff

Leading two teams of Technical Project Managers, System Architects & System Engineers, which are responsible to design and specify rail signalling solutions fulfilling customer needs based on the Thales portfolio (Route and Train Control Systems (ETCS), Field equipment, Traffic Management Systems (TMS) & ETCS On-Boad Systems (OBS)).

Technical Project Leader responsible for the European Train Control System (ETCS) Level 2 solution for the Romanian market.

Responsible for several international projects (20-30 engineers). The focus is on multi-standard Remote Radio Heads (RRH for GSM, WCDMA, WiMax, LTE).

After 7 years in the U.S. I am back in Germany. Time to return to my roots of FPGA & ASIC design. Developed several Altera/Xilinx designs for Wireless products (WiMax/LTE RRH). Worked on the implementation of a DPD (Digital PreDistortion). Responsible for the FPGA & Signal Processing Team (incl. Digital Filter & Crest Factor Reduction).

Responsible for a board/FPGA/ASIC design team and hardware qualification group. Manager for hardware projects and cost reductions. Actively involved in FPGA and Network Processor specification, development and verification. Responsible for FPGA design process, tools and automation. Experienced in leading international projects (India, Belgium, Canada, U.S.)

Responsible for the architecture, design & verification of several FPGAs (Xilinx, Altera, Lattice) for wireline products. Developed an OC-3/12 optical transport card design with full SONET / SDH termination in VHDL. Team lead for the BSP, FPGA, ASIC design group. Also created a team for Network Processor Design and developed an xDSL line card using Intel IXP2350. Introduced new tools, processes and test automation.

Design and verification of ASICs for switching applications and cable modem products. Benchmarking and introduction of new tools (e.g. C-to-VHDL conversion, SW / HDL co-simulation).

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