Böblingen

Senior Digital ASIC Development/Verification Engineer (m/f/d)

Aufgaben:

Implementation of mixed and full-custom blocks in CMOS in schematics and layout HDL coding in mixed-signal environments Support for top level and block level behavior modelling and chip level physical design Specification Based Simulations, verification on module and chip level with structural and behavior models. Analysis of circuits including process variance Performance reporting and documentation Modeling of the circuits in High Level Languages Verification of digital and analog circuits Provide guidance and advice to team members and managers Collaborate cross-functionally and maintains linkage to Chip Top-Level-, HW-, SW- and Maintenance engineering teams

Qualifikationen:

University degree, Diploma or BS EE Background in digital design (SOC), Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic knowledge about UNIX* or Linux* environment and using programming languages Technical communication, teamwork and problem-solving skills English language skills