Please apply here on "MINTbund.de" using the "Apply" link/button at the top right.

Note: Please apply exclusively via our direct application link hosted by Empfehlungsbund and MINTbund.de: https://www.mintbund.de/jobs/280553/staff-strich-principal-asic-design-engineer-m-strich-w-strich-x-in-dresden . We look forward to getting to know you!

Your tasks:

• Technical leadership of the digital design team: technical guidance, coaching and mentoring of engineers, promoting the further development and development of the team's full potential.
• Ownership of the digital and SoC architecture: significant involvement in the definition, further development and optimization of our RF system-on-chip architecture.
• Responsibility for the RTL design of complex digital blocks and their integration at system level - including technical decisions, design reviews and quality control.
• Interface function to analog/RF design, system architecture, firmware, physical design and product management - ensuring effective information flow and technically sound coordination.
• Technical strategic contributions: evaluation of new technologies, derivation of architecture decisions, identification of technical risks and development of suitable countermeasures.
• Definition of design and verification methodologies: Further development of the development and quality process, introduction of best practices and modern methods.
• Planning and implementation of functional verification at block, subsystem and chip level, including review of the verification strategy.
• Technical support for silicon bring-up, test, qualification and ramp-up of our chips.
• Development and maintenance of technical documentation, guidelines and internal standards.
• Representation of the company on a technical level towards customers, partners, foundries and external development partners.

Your profile:

• Completed studies in electrical engineering, microelectronics, computer science or a comparable field.
• At least 12-15+ years of professional experience in ASIC digital design, ideally several years in a senior, staff or principal role.
• Excellent knowledge of RTL design (SystemVerilog, Verilog or VHDL) and SoC integration of complex mixed-signal systems.
• Very good experience in chip and subsystem architecture design.
• Deep understanding of modern verification methods (constrained random, assertion-based, coverage-driven development).
• Experience in working with mixed-signal, RF or embedded software teams.
• Knowledge of synthesis, timing analysis, low-power methodologies and design-for-test is an advantage.
• Proven ability to provide technical guidance to teams, mentoring and fostering a collaborative, high performing team culture.
• Strong communication skills and enjoy acting as a technical interface within the organization.
• Very good English language skills to work in an international team on a daily basis.

We offer:

• Permanent position with a high level of personal responsibility and very good development opportunities
• Work in an international, friendly and motivated team that will be happy to support you with any questions you may have
• Flat hierarchies, openness to change and appreciation of your ideas
• An appreciative corporate culture characterized by a high degree of team spirit and trust, regular team events
• Flexible working hours (flexitime) with 1 regular home office day per week, further opportunities for mobile working by arrangement
• Attractive benefits: free job or Germany ticket or job bike (monthly flat rate of €55) + free use of the gym in the building
• Bright and comfortable offices in a central Dresden location (Plauen)
• Fast and uncomplicated application process

Based in Dresden, Germany – the heart of Silicon Saxony – we are a semiconductor startup for the breakthrough development of a new non-cellular 5G wireless chipset that enables secure massive IoT use cases.

Driven by a vision of a future where technology is seamlessly integrated into our daily lives, encompassing homes, industries, public spaces and healthcare, we strive to optimize resource and energy consumption while establishing global digital sovereignty. To realize this vision, we are actively developing a low-cost and ultra-low-power 5G wireless chipset based on the revolutionary NR+ non cellular private 5G standard.