Senior Analog ASIC Design Engineer

Senior Analog ASIC Design Engineer

Senior Analog ASIC Design Engineer

Senior Analog ASIC Design Engineer

3Brain AG

Medizintechnik

Freienbach

  • Art der Beschäftigung: Vollzeit
  • 73.000 CHF – 104.000 CHF (von XING geschätzt)
  • Vor Ort
  • Zu den Ersten gehören

Senior Analog ASIC Design Engineer

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Über diesen Job

3Brain is a Swiss deep tech company working on cell-electronic interfaces that link biological networks to computers via custom-made semiconductor microchips. Our mission is to empower life scientists to probe intelligent networks, accelerate biomedical discoveries for the benefit of patients, and create a future more exciting than the present. Our interdisciplinary team of scientists and engineers are constantly pushing the boundaries of engineering for life’s complexities. We are ambitious, fast-growing and love to explore. The company’s cutting-edge products are used in laboratories and pharma companies worldwide. 3Brain is headquartered in Switzerland nearby Zurich, has a Discovery Unit and production site in Genova, Italy, and an operational unit in the US.

Tasks

3Brain is looking for a full-time Senior Analog ASIC Design Engineer for its Swiss office to strengthen its R&D team and contribute to the next generations of our CMOS‑based biological sensor platforms. The candidate will join a group of mixed‑signal and digital ASIC engineers and will focus on designing, optimizing, and validating high‑performance analog and mixed‑signal circuits tailored for large‑scale sensor arrays.

Main responsibilities:

  • Design of analog /mixed‑signal circuit blocks for CMOS biosensor products
  • Implementation and validation of analog circuits using modern CAD tools.
  • Development of transistor‑level schematics, simulations, corner and Monte‑Carlo analyses, modelling, and layout.
  • Extraction, verification, and optimization of circuits to meet performance, area, and power requirements.
  • Documentation of design methods, specifications, architecture decisions, and verification results.Collaboration with digital, packaging, and system teams to ensure full‑chip integration and system‑level performance.

Requirements

Required Qualifications

  • 5+ years of professional experience in analog or mixed‑signal ASIC design.
  • BSc/MSc/PhD in Electrical Engineering, Microelectronics, or related field.
  • Core Expertise: Analog IC design fundamentals; Low‑noise and low‑power analog front‑end design; Stability, noise, mismatch, and linearity analysis; Device‑level simulation and modelling; Analog layout best practices
  • Proficiency with analog design workflows (i.e. schematics, state-of-the-art SPICE simulations, extraction tools, post-layout simulation, etc.)
  • Good knowledge of scripting (Python, MATLAB, or SKILL).
  • Fluency in English.
  • Strong team spirit, initiative, and ability to work independently in a multicultural environment.
  • Applicant must be authorized to work in Switzerland without employer sponsorship (e.g., EU/EFTA citizen, Swiss C permit, or family member of an EU/EFTA citizen with a work‑authorized residence card).

Additional Qualifications

  • Experience with mixed‑signal integration and top‑level verification.
  • Experience with ADC/DAC architectures and characterization.
  • Experience with physical verification (LVS/DRC, electromigration).
  • Knowledge of CMOS sensor interfaces or biomedical instrumentation is a strong plus.
  • Understanding of digital design basics and ability to collaborate with digital teams.

Benefits

  • A dynamic and stimulating work environment driven by a desire to build transformational technologies to help others.
  • A young, fast-growing company with plenty of opportunities for personal growth and development.
  • Working place: Pfäffikon SZ, Switzerland. It’s a beautiful lakeside village just outside of Zurich, the country’s main cultural, financial and business center.

To apply send your CV and short motivation letter to hr(at)3brain(dot)com, subject: Senior Analog ASIC Design Engineer.

Gehalts-Prognose

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