• Define and specify control and sequencing algorithms for PLL and clocking architectures targeting FR1 and FR2.
• Decompose 3GPP and system-level PLL requirements into detailed specifications for individual PLL building blocks.
• Define hardware/firmware algorithms with a focus on area- and timing-optimized implementations.
• Implement and simulate algorithms in MATLAB and C++.
• Develop innovative concepts to improve and optimize PLL control and sequencing behavior.
• Author detailed specifications as input to design and firmware teams.
• Perform root-cause analysis and debug issues identified during verification. Support cross-functional teams in resolving defects.

• Experience defining control sequences for digital and analog blocks within transceiver architectures.
• Strong analytical and problem-solving skills.
• Deep understanding of RF transceiver architecture, with specific expertise in frequency synthesis (PLLs, DCOs) and key metrics such as phase noise and lock time.
• Extensive hands-on experience specifying and simulating phase-locked loop (PLL) and clocking architectures.

• Solid knowledge of cellular radio standards at the physical layer (GSM, UMTS, LTE, 5G NR) and their implications for RF/PLL specifications
• Excellent written and verbal communication skills for effective cross-functional collaboration
• Experience using AI tools — such as LLMs, AI-assisted coding environments, and simulation co-pilots — to accelerate design exploration, automate repetitive analysis tasks, and improve engineering productivity
• Master's or PhD in Electrical Engineering (or equivalent) with 3+ years of relevant experience in RF/mixed-signal architectures
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