München

Description

Your responsibilities will include: - To develop and maintain verification components and test benches for chip level and block level verification including automated checking, automated coverage collection, and constrained random stimuli - To execute design verification including design and test bench debugging as well as coverage analysis and enhancements - To plan design verification and to analyse results in collaboration with design and concept engineering - To co-verify design and firmware

Minimum Qualifications

• MS/BS in Electrical Engineering, computer engineering or equivalent
• Excellent communication and interpersonal skills, combined with the ability to collaborate
• Ability to work well on a team, take ownership and motivate self and others
• Experience with Python, Perl or TCL
• Fluent English skills

Preferred Qualifications

• Advanced knowledge of verification methods and tools like UVM and System Verilog
• Good knowledge of Object Oriented Programming
• Coverage driven verification leveraging constrained random stimuli
• Assertion based verification
• Experience in Formal Verification
• Track record in digital or analog design or design debugging, preferable with mixed-signal designs