Location : Neuchâtel, Switzerland

About the Role

An innovative technology company at the forefront of ultra-low-power IC development is looking for a Senior Analog Mixed-Signal Verification Engineer to join their R&D team in Switzerland. You’ll be a key player in driving first-pass silicon success through robust mixed-signal verification methodologies.

About the Company

This organisation designs and manufactures high-performance, energy-efficient ICs used in advanced consumer, industrial, and wearable applications. Their Swiss-based engineering team combines deep analog expertise with modern verification techniques to deliver next-generation electronic systems.

Responsibilities

• Develop and implement advanced mixed-signal verification strategies across circuit and IP levels.
• Build and reuse Verilog-A behavioural models, monitors, and checkers for system-level verification.
• Collaborate with architects to define system tests and ensure functionality across all operating modes.
• Automate verification regressions using Cadence AMS Designer / Xcelium .
• Manage bug tracking, coverage analysis, and methodology improvements.
• Continuously enhance verification processes to improve time-to-market and product quality.

Profile

• Master’s degree in Electrical or Electronic Engineering (or equivalent).
• 2–3+ years’ experience in analog/mixed-signal verification or IC design.
• Solid understanding of Verilog-A / AMS verification flows .
• Strong teamwork, autonomy, and communication in a multicultural environment .
• Fluent in English ; French or German is an asset.

If you are suited and interested, please get in touch with me.