• End to end responsibility for the Defect Engineering organization
• Leading a team of around 10 defect engineers
• Define, track, and continuously improve relevant KPIs, including D0 / Defect Density; Excursion rate, wafer at risk
• Prioritize and coordinate CIP and improvement projects focused on D0 improvement
• Provide structured support to Task Force teams with resources and defect analysis expertise
• Act as first level escalation to suppliers and internal stakeholders for defect related topics
• Communicate defect relevant updates to internal and external customers
• Support internal and customer audits and drive follow up actions to closure
• Act as a role model for collaboration, ownership, and continuous improvement

• Successfully completed studies in Physics, Chemistry or Electrical Engineering or comparable
• Minimum 5 years of experience in semiconductor manufacturing, metrology, defect engineering, or related areas
• Proven leadership experience, ideally managing teams or cross‑functional groups
• Open mindset for change and the willingness to contribute to this proactively
• Strong analytical mindset with a high level of data literacy
• Deep understanding of defect inspection systems, review processes, and SPC/FDC methodologies
• Excellent communication skills with the ability to engage stakeholders at all levels
• Ability to manage priorities across multiple teams including Yield, Process, Metrology, Equipment, Manufacturing, and R&D
• Fluent English language skills, German is a plus

We offer competitive salaries and additional benefits based on your performance, experience and qualification.

The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/).
We offer a higher compensation depending on your expertise and skills.