Dr. Anastasiia Dolinina

FPGA, SoC and ASIC design. Languages and scripts: VHDL, Verilog, SystemVerilog, Python, Tcl (inkl. Vivado Batch Mode Tcl), Shell. Tools: AMD Vivado, Vivado HLS, Vivado Hardware Manager, Vivado Simulator, Mentor Graphics ModelSim, VUnit, Git. Applications: 5G, Communication Systems, Internet of Things, Embedded AI, Neuromorphic Hardware, Autonomous Driving.

FPGA, SoC and ASIC design, software. Languages: VHDL, Verilog, SystemVerilog, C, C++, Python, Tcl. Tools: Xilinx Vivado, SDK, PetaLinux, Vivado Simulator, Lattice Diamond, Intel Quartus, Mentor Graphics ModelSim, Aldec ActiveHDL, Microsoft Visual Studio, Sigasi, Git. Approaches: Code and Functional Coverage, Constrained Random Verification, Assertion based Verification. Applications: Real Time Embedded Vision Systems, 3D Stereo Vision, Positioning.

Half-year internship on Dept. of Computer Engineering and Microelectronics on Embedded Systems Architecture faculty. Program of DAAD (Deutscher Akademischer Austauschdienst) and Ministry of Education and Science of the Russian Federation called "Mikhail Lomonosov". Scientific works on the 2 topics: "Improvement of Macromodeling Approaches based on Model Order Reduction" and "Deep Learning Accelerators on FPGAs".

Work on the topic: "Order Reduction of Equations for Modeling of RF Devices". Creating new Model Order Reduction approaches to have better speed-up and accuracy of Macromodels (of amplifiers, frequency mixers, multipliers, etc.) in CAD (Computer-Aided Design) systems.

3 months collaboration on Dept. of Computer Engineering and Microelectronics on Embedded Systems Architecture faculty. HiPEAC (European Network on High Performance and Embedded Architecture and Compilation) Collaboration Grant. Title of the collaboration: "Fast points selection with piecewise local projections approach for automatic macromodel creation".

Half-year internship on Dept. of Computer Engineering and Microelectronics on Mixed Signal Circuit Design faculty. Program of DAAD (Deutscher Akademischer Austauschdienst) and Ministry of Education and Science of the Russian Federation called "Mikhail Lomonosov". Scientific works on the topic: "Macromodeling of RF Circuits based on Model Order Reduction".

Work on the topic: "Order Reduction of Equations for Modeling of RF Devices". Creating new Model Order Reduction approaches to have better speed-up and accuracy of Macromodels (of amplifiers, frequency mixers, multipliers, etc.) in CAD (Computer-Aided Design) systems.

FPGA, SoC design and software. Languages: VHDL, C. Tools: Xilinx ISE, Vivado, SDK, Lattice Diamond, Mentor Graphics ModelSim, Aldec ActiveHDL, MathWorks MATLAB. Applications: Communication Systems.

Work on the topic: "Order Reduction of Equations for Modeling of RF Devices". Creating new Model Order Reduction approaches to have better speed-up and accuracy of Macromodels (of amplifiers, frequency mixers, multipliers, etc.) in CAD (Computer-Aided Design) systems.

The topic of the thesis: "Order Reduction of Equations for Modeling of RF Devices". Main subjects: Computer-Aided Design of Integrated Circuits and Systems, Design Automation, Electronics, Mathematical Modeling, Model Order Reduction of Analog Circuits.

Main subjects: Parallel Algorithms and Computing, Optimization Methods, Control Theory, Computer-Aided Design of Integrated Circuits.

Main subjects: Electronics, Neural Networks, Modeling, Optimization Methods, Mathematical Analysis, Computational Mathematics, Mathematical Logic and Theory of Algorithms, Probability Theory, Fundamentals of Control Theory, Сomputer Networks and Telecommunications, Engineering Graphics, Database Management Systems, Operating Systems, Physics.