Dipl.-Ing. Hans Joachim Janßen

• SoC Project-Manager, aligning Sub-PJMs, creation of project-plan, escalation & solving of issues • Interacting with all teams of the project: Marketing (Market RQs), System-Eng (System & Design RQs), RTL Design (mixed lang), Func-Verif (RTL, SystemC, UVM, Emulation, FW-based), Implementation, System-Design, Cfg-Mgmt (GIT) • SoC PMO officer, definition of SoC product life cycle, phases, checklists. Initiating Milestone-Reviews & Risk-Assessment. Ramp & Rollout of planning-env and ticketing/tracking system

• Int.Team Lead: Interviewing, hiring, ramping of internal multisite team. Building Team-Structure on 2nd level (PnR, DfT, Qual, Advanced Packaging, System-Design/PCB) • Ext.Team Lead: Selection, ramp, control of ext. ASIC Vendors & SubCons • Tight interaction with HR: Job descriptions, hiring, goal setting • Ramping all aspects beyond RTL design: Synthesis, DfT (RTL, Netlist), Layout (TSMC N6 - N4), 2.5D CoWoS (HBM2e/3), Qual, System/Eval-Board • Networking (EPI, TSMC, ARM, SNPS, Mentor, ANSYS, Start-Ups)

• Project-Manager for a HW and FW Test-Environment for a 4G/5G Sub-Systems • Responsibility for tape-out critical verification tool (Algo reference model) • Definition, Bring-Up of SoC-HW CoSim methodology (Algo, SystemC, SystemVer)

• Led several escalations to solve the urgent situation, finally staffed the virtual team, • Managed the realization and pipe-cleaning of a SW delivery flow including legal aspects • Project internal SW delivery alignment manager and leader • Roll-Out and SW delivery ramp to customer in highly dynamic project environment

• Coordinated between many worldwide FW/SW teams to create and execute a Use-Case-Driven E2E feature integration verification • Interfaced and aligned with requirement engineering • Interfaced and assisted SW project-management

• Project-Manager for creation of virtual prototypes (VP) for multiple generations of a 3G L1 Sub-System as well as for a combined VP for a TDSCMA/2G/3G/4G L1 Sub-System • Alignment with and convincing of all worldwide virtual prototype teams to go for a combined VP solution for a TDSCMA/2G/3G/4G L1 Sub-System • Established new communication methods to foster team-communication as well as introducing new configuration-management

• Disciplinary lead of Logical and Physical Synthesis (LPS) group in Duisburg • Project Management for Circuit-Synthesis and Layout design for 3G baseband SoCs • Responsibility for the efficiency of the development-tools involved in the flow (e.g. introduced configuration management for large size LPS data) • Technical education for staff members worldwide • Project Management for System-Project XG613 including budget-responsibility and controlling • Leading teams in critical phases

• Evaluation and development of new implementation-methodologies & tools • Support of SoC teams by performing logical synthesis, timing-verification and equivalence-verification • Project Manager and methodology owner for a memory redundancy flow solution covering aspects of all project phases • Project Manager and methodology owner for a fully new 3G firmware trace tool, roll-out across world-wide project-teams and customer • Task-Force-Lead for area- and cost-reduction for a 3G SoC

• Responsibility for the coordination of all activities between the analog-design-team in Munich and digital-design-team in Duisburg • Continuous alignment with product-definition-team • Integration responsibility and project alignment with SoC toplevel team in San Jose • Bring-Up and debugging in San Jose incl. coding and provisioning of Tcl/Tk-Bring-Up-GUI

• Responsibility for concept and implementation of the SoC toplevel for a wireline 10GBit physical layer device • Included embedding and development of a customized microcontroller subsystem as well as the bus-interface towards all peripherals • Concept and implementation of a MDIO interface based on IEEE 802.3ae standard

• Development of components for a synthesize-able verification environment to verify an ATM-Controller for UMTS networks • Mapping of verification environment to multiple FPGAs • Bring-Up, debugging and execution of a system-verification, jointly with the verification-team (VHDL/C Co-Simulation, hardware-accelerated verification on IKOS with attached FGPA verification environment)

• Functional verification of several subblocks of a videotext controller SoC • Conceptual design and implementation of an interface between videotext controller and an external memory device • Support and debugging of multiple variants of a multi-chip-module (controller and memory on different substrate types / suppliers)

Diploma-Thesis "Creation of a design-rule and variable standard-cell-library". Design of first ever full-custom microchip of technical college.