Dipl.-Ing. Hans Joachim Janßen

Project/Design/Team-Manager & Leader (ASIC, SoC Chip Design)

Angestellt, Director of implementation engineering, SiPearl

Hamburg, Germany

Skills

Projektmanagement
ASIC
Interkulturelles Management
Cross-Discicpline Project/Metholodogy BringUp
Projektplanung
Project management
IPMA
Team Management
Teamleitung
Teamfähigkeit
Business Line Management
Personalführung
intercultural competence
Interkulturelle Kompetenz
Intercultural management
Cross-Functional Teamlead
Intercultural Communication
Interkulturelle Kommunikation
Virtual team
Virtuelles Team
Customer Service
Kundenservice
Semiconductor
IC Design
VLSI
System on Chip
SoC
Field Programmable Gate Array (FPGA)
FPGA
Virtual Prototypes
Virtuelle Prototypen
Hardware Architecture
Integrated Circuit Design
Entwurf Integrierter Schaltungen
Halbleiterindustrie
RTL-Design
Functional Verification
Simulations
Debugging
Configuration Management
Konfigurations-Management
Clear Case
Git
VHDL
verilog
SystemVerilog
SystemC
C
C++
Perl
Tcl/Tk
Python
Low Power Design
Toplevel Design
DfT
3G
UMTS
4G
LTE
5G

Timeline

Professional experience for Hans Joachim Janßen

  • Current 2 years and 9 months, since Aug 2021

    Senior Project-Manager (European HPC CPU)

    SiPearl

    • SoC Project-Manager, aligning Sub-PJMs, creation of project-plan, escalation & solving of issues • Interacting with all teams of the project: Marketing (Market RQs), System-Eng (System & Design RQs), RTL Design (mixed lang), Func-Verif (RTL, SystemC, UVM, Emulation, FW-based), Implementation, System-Design, Cfg-Mgmt (GIT) • SoC PMO officer, definition of SoC product life cycle, phases, checklists. Initiating Milestone-Reviews & Risk-Assessment. Ramp & Rollout of planning-env and ticketing/tracking system

  • Current 3 years and 9 months, since Aug 2020

    Director of implementation engineering

    SiPearl

    • Int.Team Lead: Interviewing, hiring, ramping of internal multisite team. Building Team-Structure on 2nd level (PnR, DfT, Qual, Advanced Packaging, System-Design/PCB) • Ext.Team Lead: Selection, ramp, control of ext. ASIC Vendors & SubCons • Tight interaction with HR: Job descriptions, hiring, goal setting • Ramping all aspects beyond RTL design: Synthesis, DfT (RTL, Netlist), Layout (TSMC N6 - N4), 2.5D CoWoS (HBM2e/3), Qual, System/Eval-Board • Networking (EPI, TSMC, ARM, SNPS, Mentor, ANSYS, Start-Ups)

  • 2 years and 6 months, Feb 2018 - Jul 2020

    Senior Project-Manager Test-Environment (4G/5G Baseband)

    Intel Corp.

    • Project-Manager for a HW and FW Test-Environment for a 4G/5G Sub-Systems • Responsibility for tape-out critical verification tool (Algo reference model) • Definition, Bring-Up of SoC-HW CoSim methodology (Algo, SystemC, SystemVer)

  • 1 year and 1 month, Jan 2017 - Jan 2018

    Software Delivery Manager (3G/4G Baseband & GNSS SoC)

    Intel Corp.

    • Led several escalations to solve the urgent situation, finally staffed the virtual team, • Managed the realization and pipe-cleaning of a SW delivery flow including legal aspects • Project internal SW delivery alignment manager and leader • Roll-Out and SW delivery ramp to customer in highly dynamic project environment

  • 10 months, Mar 2016 - Dec 2016

    Feature Integration Lead (3G/4G Baseband & GNSS SoC)

    Intel Corp.

    • Coordinated between many worldwide FW/SW teams to create and execute a Use-Case-Driven E2E feature integration verification • Interfaced and aligned with requirement engineering • Interfaced and assisted SW project-management

  • 5 years and 1 month, Feb 2011 - Feb 2016

    Senior Project Manager Virtual Prototype (TDSCMA/2G/3G/4G L1 SubSystem)

    Intel Corp.

    • Project-Manager for creation of virtual prototypes (VP) for multiple generations of a 3G L1 Sub-System as well as for a combined VP for a TDSCMA/2G/3G/4G L1 Sub-System • Alignment with and convincing of all worldwide virtual prototype teams to go for a combined VP solution for a TDSCMA/2G/3G/4G L1 Sub-System • Established new communication methods to foster team-communication as well as introducing new configuration-management

  • 3 years and 2 months, Dec 2007 - Jan 2011

    Engineering manager LPS & Senior Project-Manager (Wireless SoCs)

    Infineon Technologies

    • Disciplinary lead of Logical and Physical Synthesis (LPS) group in Duisburg • Project Management for Circuit-Synthesis and Layout design for 3G baseband SoCs • Responsibility for the efficiency of the development-tools involved in the flow (e.g. introduced configuration management for large size LPS data) • Technical education for staff members worldwide • Project Management for System-Project XG613 including budget-responsibility and controlling • Leading teams in critical phases

  • 3 years and 10 months, Feb 2004 - Nov 2007

    Project Manager & Senior Staff Digital Design Methodology (Wireless SoCs)

    Infineon Technologies

    • Evaluation and development of new implementation-methodologies & tools • Support of SoC teams by performing logical synthesis, timing-verification and equivalence-verification • Project Manager and methodology owner for a memory redundancy flow solution covering aspects of all project phases • Project Manager and methodology owner for a fully new 3G firmware trace tool, roll-out across world-wide project-teams and customer • Task-Force-Lead for area- and cost-reduction for a 3G SoC

  • 1 year and 6 months, Aug 2002 - Jan 2004

    Project Manager (10GBit XAUI/SFI42 Mixed-Signal Macro)

    Infineon Technologies

    • Responsibility for the coordination of all activities between the analog-design-team in Munich and digital-design-team in Duisburg • Continuous alignment with product-definition-team • Integration responsibility and project alignment with SoC toplevel team in San Jose • Bring-Up and debugging in San Jose incl. coding and provisioning of Tcl/Tk-Bring-Up-GUI

  • 1 year and 7 months, Jan 2001 - Jul 2002

    Staff Design Engineer (10GBit L1 Device)

    Infineon Technologies

    • Responsibility for concept and implementation of the SoC toplevel for a wireline 10GBit physical layer device • Included embedding and development of a customized microcontroller subsystem as well as the bus-interface towards all peripherals • Concept and implementation of a MDIO interface based on IEEE 802.3ae standard

  • 1 year, Jan 2000 - Dec 2000

    Senior Verification Engineer (ATM/UMTS Controller)

    Infineon Technologies

    • Development of components for a synthesize-able verification environment to verify an ATM-Controller for UMTS networks • Mapping of verification environment to multiple FPGAs • Bring-Up, debugging and execution of a system-verification, jointly with the verification-team (VHDL/C Co-Simulation, hardware-accelerated verification on IKOS with attached FGPA verification environment)

  • 1 year and 4 months, Sep 1998 - Dec 1999

    Verification Engineer (Videotext-Controller)

    SIEMENS

    • Functional verification of several subblocks of a videotext controller SoC • Conceptual design and implementation of an interface between videotext controller and an external memory device • Support and debugging of multiple variants of a multi-chip-module (controller and memory on different substrate types / suppliers)

Educational background for Hans Joachim Janßen

  • 4 years and 1 month, Sep 1994 - Sep 1998

    Applied Microelectronics

    Fachhochschule Wilhelmshaven

    Diploma-Thesis "Creation of a design-rule and variable standard-cell-library". Design of first ever full-custom microchip of technical college.

  • 2 years and 11 months, Aug 1989 - Jun 1992

    Communication electronics radio engineering

    Marinearsenal Wilhelmshaven

Languages

  • English

    Fluent

  • German

    First language

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