
Harini Siddaiah
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Harini Siddaiah
- Bis heute 7 Jahre, seit Mai 2019
Lead Engineer Senior
Qualcomm Inc.
• Install, configure and customize external foundry PDKs (TSMC, UMC, SEC, GF) across various technology nodes viz. 180nm to 3nm • Validation of foundry PDK • Migration of design across different technology nodes using SKILL • Evaluation, Enablement and support of CAD tools, flow and features viz. Totem-Pathfinder, Totem-EMIR, customsimRA, SDR, Modgen • Scripts to develop utility and support designers • Provide user support to worldwide design centers
- 2 Jahre, Juni 2017 - Mai 2019
MTS, EDA Engineer
Maxim Integrated
A new team was formed in India in PDK domain. I am the first member to join the new team in Bangalore. Mainly focused -- > To develop/lead team in India. Collaborate with co-team working in USA. > Develop, migrate, support various technology nodes of Maxim foundry. > Attend customer issues on time and help/train customers in using PDK.
I worked as PDK developer. Involved in development and support PDK(process design kit) for various technology nodes. Involved in developing dashboards for customers to view the result of PDK test runs. Worked in development and integration of automating PDK test runs into Jenkins environment.
Responsible for Pcell development. Pcell is a Parameterized Cell contains a user defined ‘evaluation procedure’ and set of ‘parameter values’ to derive a desired implementation of an instance. Create Symbols, Simulation views, attaching CDF & Simulation information, generating ivpcell view and if needed modification in netlisting procedures. Written new callbacks and edited existing callbacks.
I worked as Student Intern for a period of 12months. My project was on "XOR System" development. This is a system, which helps to evaluate new developed PDK w.r.t immediate previous versions to see if there are any undesired changes. The system is automated system. Developed using SKILL and PERL.
Ausbildung von Harini Siddaiah
- 1 Jahr und 11 Monate, Aug. 2010 - Juni 2012
VLSI Design and Embedded Systems
WINGS: SJCE, Mysore,India
VLSI Process Technology, CMOS design and circuits,SOC design, Low Power VLSI Design, Digital VLSI design, VLSI Design Automation, VLSI Testing and verification, RTOS, CMOS RF Design, CMOS for Analog and Mixed signal
- 4 Jahre, Juli 2004 - Juni 2008
Electronics & Communication
The National Institute of Engineering, Mysore
Maths, VHDL, Verilog, VLSI, Analog and digital communication, wireless communication, signals and sytems, control systems
Sprachen
Englisch
C1 (Fließend)
Deutsch
A1-A2 (Grundkenntnisse)
Japanisch
A1-A2 (Grundkenntnisse)
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