Josef Schmid

ist nur teilweise verfügbar.

Freiberuflich, Freelancer ASIC/FPGA/VHDL (Radiation/TID/Stress/Aging/ROSC, DelayLines/LiDAR), Ing.-Büro Josef Schmid

Neumarkt in der Oberpfalz, Germany

Skills

* VHDL-Design & Rapid Prototyping (FPGA/ASIC VHDL
* Reliability: Wearout & Aging effects
* Radiation Effects: TID & Soft Errors (SEU/SET/TM
* Automation & Scripting (Tcl/Tk Python)
* Conferences & Workshops: ITC ANALOG TUZ SNUG
* ASIC System & CoSimulation (VHDL-RTL/AMS/RNM Ve
* HW/SW Fault Injection & Analysis
* Design for Test (DFT SCAN ATPG ATE JTAG BIS
* more infos at www.jjschmid.de and www.jjschmid.d

Timeline

Professional experience for Josef Schmid

  • Current 2 years and 3 months, since Mar 2022

    Freelancer ASIC/FPGA/VHDL (Radiation/TID/Stress/Aging/ROSC, DelayLines/LiDAR)

    Ing.-Büro Josef Schmid

    Reviews&Training (VHDL/AMS, Tcl, TID, Aging, LiDAR), RTL-Design, Testbench&Simulation, Regression&Automation, ROSC&AgingMonitors, DelayLines@LiDAR, Tooling (Modelsim, Libero, Vivado), Evaluation&Recherche

  • 3 years and 11 months, Apr 2018 - Feb 2022

    Senior Expert ASIC/FPGA/VHDL

    iSyst - intelligente Systeme GmbH

    * VHDL-Design & Rapid Prototyping (FPGA/ASIC, VHDL/AMS/Verilog) * Reliability: Wearout & Aging effects * Radiation Effects: TID & Soft Errors (SEU/SET/TMR) * Automation & Scripting (Python, Tcl/Tk)

  • 10 years and 5 months, Nov 2007 - Mar 2018

    Projektingenieur

    iSyst - intelligente Systeme GmbH

    * HiL-Testsysteme (Hardware in the Loop) * Testautomatisierung (Matlab, Simulink, Python) * VHDL-Design & Rapid Prototyping (FPGA/ASIC) * Design for Test (DFT, ATPG, ATE, JTAG, Scan etc.) * ParaObsol - Obsoleszenz Management * RedunSys - Redundante Systeme (TMR): radiation effects, aging (TID) & soft errors (SEU/SET) * HW/SW Fault Injection, JTAG PinFaking * SystemSimulation (Saber/Cosimulation: VHDL_AMS, MAST, Verilog) * Automation & Scripting (Python, Tcl/Tk)

  • 1 year and 10 months, 2006 - Oct 2007

    Entwicklungsingenieur

    Alcatel-Lucent

    ASIC/ASSP/FPGA Design&Test, DFT Items (SCAN; BIST, JTAG), SOC Architectures, Registermap Implementation, Controller Interfaces (CTLID, MPC, RapidIO), Quality Electronic Design, Soft error rate, jtag pinfaking

  • 1998 - 2006

    Entwicklungsing.

    Lucent Technologies, Bell Labs

    ASIC/ASSP/FPGA Design&Test DFT, SOC architecture Registermap Implementation Controller Interfaces QED, SER, RIO

  • 1997 - 1997

    Entwicklungsing.

    AT&T, Bell Labs

    ASIC Design&Test

  • 1983 - 1996

    Entwicklungsingenieur

    Philips Kommunikations Industrie

    ASIC Design&Test

  • 4 months, Oct 1981 - 1982

    Entwicklungsingenieur

    TEKADE

    ASIC Design&Test

Educational background for Josef Schmid

  • 3 years and 10 months, Oct 1977 - Jul 1981

    Elektrotechnik

    OTH Regensburg

    Nachrichtentechnik

Languages

  • German

    -

  • English

    -

Interests

Family
Natur & Garten
Hildegard von Bingen

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