Josef Schmid

* Architecture, Design, Integration & Verification * Research Projects

Reviews&Training (VHDL/AMS, Tcl, TID, Aging, LiDAR), RTL-Design, Testbench&Simulation, Regression&Automation, ROSC&AgingMonitors, DelayLines@LiDAR, Tooling (Modelsim, Libero, Vivado), Evaluation&Recherche

* VHDL-Design & Rapid Prototyping (FPGA/ASIC, VHDL/AMS/Verilog) * Reliability: Wearout & Aging effects * Radiation Effects: TID & Soft Errors (SEU/SET/TMR) * Automation & Scripting (Python, Tcl/Tk)

* HiL-Testsysteme (Hardware in the Loop) * Testautomatisierung (Matlab, Simulink, Python) * VHDL-Design & Rapid Prototyping (FPGA/ASIC) * Design for Test (DFT, ATPG, ATE, JTAG, Scan etc.) * ParaObsol - Obsoleszenz Management * RedunSys - Redundante Systeme (TMR): radiation effects, aging (TID) & soft errors (SEU/SET) * HW/SW Fault Injection, JTAG PinFaking * SystemSimulation (Saber/Cosimulation: VHDL_AMS, MAST, Verilog) * Automation & Scripting (Python, Tcl/Tk)

ASIC/ASSP/FPGA Design&Test, DFT Items (SCAN; BIST, JTAG), SOC Architectures, Registermap Implementation, Controller Interfaces (CTLID, MPC, RapidIO), Quality Electronic Design, Soft error rate, jtag pinfaking

ASIC/ASSP/FPGA Design&Test DFT, SOC architecture Registermap Implementation Controller Interfaces QED, SER, RIO

ASIC Design&Test

ASIC Design&Test

ASIC Design&Test

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