Md Sazzad HOSSAIN

[0.13 µm SiGe BiCMOS] + D-band TX-AGC + Band-gap Reference circuits; LDOs + AGC front-end D-band 4-channel TRX with IQ Mismatch Calibrator + Schematics and Layout Verifications- Full D-band TRX System + PGA for RX Baseband Signal Processing + D-band On Board/On-Chip Antennas and Ribbon Bond Interconnects + 120GHz and 160GHz On-Chip Antenna Design for Radar TRX-Cascaded Radar + 120GHz, 160GHz MIMO Radar Antenna Design on Si-Interposer Tech with Flip-Chip Interconnects + Multi-layer RF PCB design

Electronic Circuit Design Team [0.25um SiGe BiCMOS IHP Microelectronics Process] + Schematics and Layout Verification, re-design (Top-Level Electronic ICs, 100G Electro-Optical TRX Project) + Understanding the Electro-Optical Interconnects in 100Gb/s PAM4 TX for Server Interconnects

[0.13 µm CMOS TSMC Process] + N-PLL design at 2.4GHz based on Fast Locking Event-Driven Model for IoT Applications. +Fast-lock PLL Simulator development and system-based engineering support-Fraunhofer ENAS, Germany [0.35um CMOS AMS Process] + High-Frequency Transformer and Solenoid Inductor Design [28nm FDSOI CMOS ST Microelectronics Process] + Frequency Synthesizer/Caliper PLL Design at 4.7GHz-6.3GHz (4 times Freq.) for Global Navigation Satellite System and 5.16GHz-5.72GHz WiFi Applications.

Dept. of Electrical and Electronic Engineering Micro-electronics Circuits+ Sessional/Lab

Dept. of Electrical and Electronic Engineering Micro-electronics Circuits+ Sessional/Lab; VLSI Design+ Sessional/Lab; Electromagnetism; Wireless Communication

Semiconductor Process-55 CMOS Fujitsu, 40nm CMOS TSMC; - Analog Schematics and Layout Design-60GHz and 79 GHz Transformer Coupled Amplifier - Millimeter-Wave Transformer Design (Stacked and Planner Type) - L-C-L Coupled and Transformer Coupled Matching Network, LNA, PA (Basic Understanding) - MATLAB Modeling, Simulation, and Optimization - EM Simulation of Small Transformer at MOMENTUM and HFSS - 3dB BW, High Gain Amplifier, Noise Analysis, Noise Figure, Output Power, PAE

-Awarded, Marks: 80 percentile (above), CGPA: 3.94/4.00 [calculated on US Scale]; M.Sc. Thesis (Device): “Design of CMOS On-Chip Transformers for Millimeter-Wave Amplifiers”. [Fujitsu DDC 55nm CMOS]

- 1st Class, Marks: 70.80 Percentile, CGPA:3.34/4.00; B.Sc. Thesis (System):” Future Internet Technologies: Hybrid CO-OFDM TWDM PON and WLAN System for FiWi Amelioration; [4G LTE-A, Passive Optical Network, MATLAB Simulation]