Simona Bernardi

Design and Verification of OMAP NoC interconnects with state of the art third party tools (Arteris/Sonics), using OCP/AMBA protocols. Design Lead of MIPI Low Latency Interface IP: design, verification, protocol compliance, system level integration/debug, management of 3rd Party IP scheduling. Participation to MIPI LLI standard definition 1.0 Design of DRAM memory management unit based on HLS Esterel

ESL methodology support for Behavioral Synthesis and IP Functional modeling for Pre-Si platforms for SW development. Previously working on :SystemC modeling, Virtual Platform solutions for early SW development, evaluation of Coware tools and methodology for Virtual Platform for SW development and fast ISA models development.

Architecture specification, VHDL design and validation of NOKIA Wireless SoC designs, based on ARM7, ARM1176 and TI C55 processors. Formal verification tool support for NOKIA business unit (Esterel, TRANSEDA) Evaluation of Esterel language and Esterel Technologies tools for behavioral synthesis and formal verification. Joint work with Esterel Technologies for the introduction and validation of multi-clocks to Esterel Language. Publications: - Best Paper Award SAME 2004: “Multiclock Design and Synthes

Architecture specification, RTL design, validation and STA analysis of Ericsson MicroWave Modem ASICs and corresponding FPGA prototypes (XILINX, ALTERA). Validaton of modem components against MATLAB fixed point models. Evaluation of ALTERA FPGA solutions embedding ARM9 processors. Evaluation of alternative synthesis tools for FPGA design. Definition/implementation of floating point alternative architecture for modem components (equalizer, frequency loops), optimized for RTL synthesis.

Digital design and verification of fiber optics ATM ASIC components. Evaluation of EDA tools for behavioral synthesis.