
Suei Feng Chen
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Suei Feng Chen
- Bis heute 15 Jahre und 11 Monate, seit Aug. 2009
Electronic R&D enginner
Orbit Optotech Inc.
* DMX512 and ArtNet system setup, SMD LED(RGBW) lighting fixture hardware design(components survey and set up BOM), debug, compliance test, QA and production. Projects' system diagram planning. CE, ETL, EMI, safety ... certification handling. Prepare and write Technical documents and report of products. Interested in new products design and lighting system planning.
Overseas Sales(Asia, Europe, America): sales, exhibition contact Wifi engineering support: antenna performance testing
- 1 Jahr und 1 Monat, März 2005 - März 2006
Principal engineer
LITEON
Job Function: Principal engineer (SW R&D Dept., Communications SBG) - Analyzing GSM’s & GPRS’s protocol, and relative product validation Job Function: Principal engineer (DQA, Consumer electronics Solutions SBU, Digital Convergence Solution SBG) - DVB-T tuner Design & Quality Assurance and customer service
- 4 Jahre und 4 Monate, Juli 1999 - Okt. 2003
Supervisor
Taiwan Cellular Corp.
- Supervising the operation and equipments of Base Station System(BSS) part of D1800 Mobile Phone system(GSM 2G) - Managing several network re-plans and operations of BSS part (GSM)
- 1 Jahr und 11 Monate, Juni 1997 - Apr. 1999
Testing Engineer
Siemens Telecommunication Systems Limited(Taiwan)
Support Mobile Phone system D1800 GSM (2G), Base Station System Installation, testing, debug and maintenance for Taiwan Mobile company
Ausbildung von Suei Feng Chen
- 7 Monate, Juni 2007 - Dez. 2007
Embedded software design
Yen Tjing Ling Industrial Research Institute, National Taiwan University
Verilog, Quartus II and NIOS II (ALTERA DE2 FPGA), Cygwin, CCS (TI DSP 55xx, 54xx) Special topic: SOC design,Verilog programming.Design 64 bits CRC4,8,12,16,32 encode-decode circuit & system using uClinux onAltera DE2 FPGA platform.
- 7 Monate, Mai 2004 - Nov. 2004
Analog and Mixed-Signal IC Design
Yen Tjing Ling Industrial Research Institute, National Taiwan University
VLSI design. VLSI Testing and Design for Testability. Analog Integrated Circuits Design. Advanced Analog Integrated Circuits Design, Matlab Mixed signal IC Layout, Cadence, Calibre, Hspice. Special Topic: MDLL(Multiplying Delay Locked Loop)
- 7 Jahre und 10 Monate, März 1989 - Dez. 1996
Electronic Engineering
National University of Córdoba, Argentina
Specialization: automatic control system and technique Master thesis: Implementation of Digital Lock-In Amplifier (using AT&T DSP and its Assemble, Borland C++, FIR/IIR)
Sprachen
Englisch
Gut
Spanisch
Fließend
Chinesisch
Muttersprache
Deutsch
Grundlagen
Taiwanese
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