Suneetha Raja
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Suneetha Raja
- Bis heute 9 Jahre und 8 Monate, seit Okt. 2015
Senior RF IC Layout Consultant
Huawei Technologies
- Millimeter Wave Layout of 54GHz PAM4 in ST 55nm BiCMOS. - Layout design of RF SAR ADC, LDOs in SMIC 14nm FinFet. - Full chip Layout of RF Custom Digital PA in SMIC 40nm. - Layout design of RF SAR ADC, PLL, VCO and LDOs in TSMC 16nm FinFet. - Full chip Layout of RF Custom Digital PA in GF 22nm FD-SOI. Interfaced with GF for the PDK issues. - Layout of RF blocks like LNA, Programmable LPF and VGA,RX BB, LDO, Digital TX and PA for 5G Base Stations in TSMC 28nm. - Full chip Layout of RF FEM,LNA in TSMC 130nm.
- 11 Monate, Nov. 2014 - Sep. 2015
RF/Mixed Signal IC Layout Consultant
Intel Corporation
- Layout design of high speed RF and Mixed Signal blocks like ADC, TX, DCDC and PMU for a Flip chip in Deep Sub-micron 65nm and 28nm Intel flavored TSMC Processes. - Complete Verification (LVS/DRC) of design using Calibre verification tools. - Tapeout QC checks like Antenna, Density, ERC, ESDNET using Calibre tools. - Version control of Cadence Open access database using Clearcase and Synchronicity.
- 3 Monate, Aug. 2014 - Okt. 2014
RF IC Layout Engineer
Kandou Bus S.A.
Working as a RF IC Layout Consultant on a 28nm project.
- 3 Monate, Mai 2014 - Juli 2014
Analog IC Layout Consultant
NXP Semiconductors
- Layout design of various Analog and Mixed-Signal modules in an Automotive project using Cadence Open access and Virtuoso XL in A-BCD9 SOI 0.14um Technology Process. - Complete verification (LVS/DRC/DRC_antenna/DRC_HV/ERC) of blocks using PVS verification tools. - Version control of Open access database using DesignSync Design management system.
- 2 Monate, März 2014 - Apr. 2014
IC Layout Consultant
Samsung Electronics
- Layout design of various RF and Mixed-Signal Modules like prescaler, rfpll and various regulators, LDOs using Cadence Open access and Virtuoso XL in Deep Sub-micron Global Foundaries 65nm Process. - Complete Verification (LVS/DRC/Antenna/ERC) of block and Chip layouts using PVS verification tools. - Version control of Open access database using SOS Design management system.
- 6 Monate, Sep. 2013 - Feb. 2014
IC Layout Consultant
Dialog Semiconductor
- Layout design of various Analog Mixed-Signal Modules, RF pads and Test structures by using Cadence Open access and Virtuoso XL in Deep Sub-micron TSMC 55nm Process. - Providing support and co-ordination on Radio layout for the project between various sites. - Complete Verification (LVS/DRC/Antenna/ERC) of Layout using Calibre verification tools. - Perform Layout reviews on various modules and identifying potential problems. - Version control of Open access database using Synchronicity.
- 3 Monate, Juli 2013 - Sep. 2013
IC Layout Consultant
NXP Semiconductors
Layout design and co-ordination for Top level chip layout and modules like LDOs, VREG, DABL and DAB3 on TSMC 65nm process using Cadence Virtuoso (Cadence 5). Verification (LVS/DRC) of design using PVS verification tools. Tapeout QC checks like Antenna and ERC. DFM layout checks of modules and identifying potential problems.
- 4 Monate, März 2013 - Juni 2013
RF/Mixed Signal IC Layout Consultant
Kisel Microelectronics AB
- 4 Monate, Dez. 2012 - März 2013
Analog-Mixed Signal IC Layout Consultant
Samsung Electronics
- 8 Monate, Apr. 2012 - Nov. 2012
IC Layout Consultant
Intel Mobile Communications
- 6 Jahre und 4 Monate, Okt. 2005 - Jan. 2012
IC Layout Design Engineer
Texas Instruments Ltd
- 1 Jahr und 6 Monate, Mai 2004 - Okt. 2005
IC Layout Engineer
Intel Technology India Pvt Ltd
- 1 Jahr und 7 Monate, Nov. 2002 - Mai 2004
IC Layout Engineer
Sasken Communication Technologies Ltd
Worked at a client site - ATI Technologies, now part of AMD, Toronto, CANADA.
- 1 Jahr, Nov. 2001 - Okt. 2002
IC Layout Engineer
Advanced Micronic Devices Ltd
Worked at a client place by name Texas Instruments, located in Bangalore, INDIA.
Sprachen
Englisch
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