Surbhi Bansal

Working as DFT/Test lead on SoC designs: DFT activities included defining SoC test architecture, scan patterns generation using atpg tools, memory testing using bist, jtag pattern generation, BSR cells integration, and verification of all the above patterns using simulation tools. Test activities involved testing SoC on Teradyne J750 tester. Building test program for SoC for both DFT and functional patterns, pattern conversion and cyclization and simulation using internal tools.