Vaibhav Bhatnagar
Angestellt, Research Engineer, IRISA
Lannion, Frankreich
Werdegang
Berufserfahrung von Vaibhav Bhatnagar
Bis heute 10 Jahre und 10 Monate, seit Dez. 2013
Research Engineer
IRISA
• Development of FPGA based software defined radio (SDR). • Develop, test, and verify wireless protocols (PHY layer) using Matlab, RTL for SDR. • Survey of Vehicular communication (V2X) for different SDR. • Performance evaluation of ZigBee transceiver on Nutaq-Perseus-6010 SDR.
2 Jahre und 1 Monat, Dez. 2011 - Dez. 2013
Research Engineer
INRIA
•Development of FPGA based flexible software defined radio (smart node). •Development of different DSP algorithm using RTL and simulate them on ModelSim, ISE design suite for Xilinx FPGA platforms. •Development and implementation of end-to-end IEEE 802.15.4 (ZigBee) transceiver on SDR •Development of wireless protocols using High Level Synthesis (HLS) tools e.g. CatapultC. •Development of PLB and AXI4 based IPs in Xilinx Platform Studio for physical (PHY) layer in context of XC6VLX240T FPGA.
Ausbildung von Vaibhav Bhatnagar
1 Jahr und 10 Monate, Aug. 2005 - Mai 2007
Electrical Engineering
University of Bridgeport, Bridgeport, CT, USA
Digital Signal Processing Bio-Signal Processing Mobile Communication Pattern Recognition Analog VLSI Digital VLSI Computer Architecture
4 Jahre und 2 Monate, Juni 2000 - Juli 2004
Electronics and Communication
Uttar Pradesh Technical University, Lucknow, UP, India
Digital Signal Processing Analog Communication Digital Communication Telecommunication Digital Integrated Circuits Analog Integrated Circuits VLSI
Sprachen
Englisch
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