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Last Mile Semiconductor GmbH, a Dresden-based deep-tech start-up, is developing the next generation of energy-efficient wireless connectivity solutions based on the new DECT NR+ standard. As a pioneer in the field of ultra-low power RFICs and SoCs, we are shaping the future of IoT, Industry 4.0 and Massive Machine-Type Communication (mMTC). Our chips are based on modern CMOS and FD-SOI technologies and are used worldwide for scalable, robust and cost-efficient applications. To strengthen our team, we are looking for an experienced person in the field of IC layout who will make a significant contribution to the success of our tape-outs.

Your role
As a Senior Layout Engineer, you will be responsible for the physical design of highly integrated RF and mixed-signal ICs - from the initial floorplan idea to the successful tape-out. You will work closely with our RFIC, analog, digital and system teams and bring your expertise to complex layout challenges.

Your tasks

• Independent design of IC layouts for RF, analog and mixed-signal blocks
• Implementation of high-performance layout techniques (matching, symmetry, shielding, parasitics control)
• Creation of floor plans and block-level layouts for complex SoCs
• Implementation of layout verification (DRC, LVS, ERC)
• Setting up and operating advanced layout tools (parasitic extraction, electromigration and IR drop)
• Close cooperation with design engineers to optimize performance and yield
• Analyzing and debugging layout related issues during the verification and bring-up phase
• Support of tape-out activities
• Collaboration in the further development of layout guidelines and methodologies
• Documentation and know-how transfer within the team

Technologies & Standards

• RFIC design & layout
• Mixed-signal IC design
• CMOS / FD-SOI technologies (22FDX)
• DECT NR+ wireless standard
• EDA Tools: Cadence Virtuoso, Calibre (DRC/LVS/PEX), Assura
• Parasitic Extraction & EM Awareness
• Analog Layout Techniques: Matching, Common-Centroid, Guard Rings
• Low-Power Design & Ultra-Low-Power Architectures
• Tape-out Flow & Foundry Interfaces

Your profile

• Degree in electrical engineering, microelectronics or similar
• Several years of experience in IC layout (analog / RF / mixed-signal) - ideally in an industrial environment
• Deep understanding of:
• Layout parasitics and their influence on performance
• Matching strategies and layout optimization
• Substrate noise, crosstalk, EM effects
• Confident with Cadence layout tools and verification flows
• Experience with advanced technology nodes (CMOS / FD-SOI) an advantage
• Structured, precise and quality-oriented way of working
• Ability to work in a team and strong communication skills in interdisciplinary teams
• Good knowledge of English (German an advantage)

We offer:

• Permanent position with a high level of personal responsibility and very good development opportunities
• Work in an international, friendly and motivated team that will be happy to support you with any questions you may have
• Flat hierarchies, openness to change and appreciation of your ideas
• An appreciative corporate culture characterized by a high degree of team spirit and trust, regular team events
• Flexible working hours (flexitime) with 1 regular home office day per week, further opportunities for mobile working by arrangement
• Attractive benefits: subsidized job or Germany ticket or job bike (monthly flat rate of €55) + free use of the gym in the building
• Bright and comfortable offices in a central Dresden location (Plauen)
• Fast and uncomplicated application process

Employee benefits

Based in Dresden, Germany – the heart of Silicon Saxony – we are a semiconductor startup for the breakthrough development of a new non-cellular 5G wireless chipset that enables secure massive IoT use cases.

Driven by a vision of a future where technology is seamlessly integrated into our daily lives, encompassing homes, industries, public spaces and healthcare, we strive to optimize resource and energy consumption while establishing global digital sovereignty. To realize this vision, we are actively developing a low-cost and ultra-low-power 5G wireless chipset based on the revolutionary NR+ non cellular private 5G standard.