• Responsibilities include especially, but are not limited to: Lead the complete DfT solutions in a chip design by working with chip DfT team to detail DfT specifications, and define the SoC test interface Develop and implement DfT architecture as well as generate structural test vectors, analyze and improve coverage Work with the validation team, the design team and testing team for different DfT topics.

• • You hold a Bachelor or Master's in Electrical / Computer Engineering, or equivalent strong experience.
• • Ability to fluently speak and write in English.
• • We are counting on your expertise and knowledge about industrial standards and practices in DfT, including ATPG (debug, compressed patterns), JTAG/1500 debug, MBIST and trade-offs between test quality and test time.

• • You have experience developing DfT specifications and driving DfT architecture and methods for designs.
• • You are confident with Verilog and / or VHDL, and have experience with simulators and waveform debugging tools.
• • By now you are demonstrating proven understanding of design verification (DV) methodologies for validating DfT implementation in simulation pre-silicon.
• • You have experienced with STA constraints development and analysis for DfT modes and SDF simulations.
• • You love conducting experiments during silicon debug, capturing and analysing data; and utilise scripting to support efficient handling of ATE data.

At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.