Abhijith Rao

Memory verification. Working in pseudo dual port memories. Setting testbench for espcv verification. Verifying functionalities like Scan, Bypass, ATPG shift, Row redundancy, Column redundancy, Write-read, write-read with address out of range. Cross verifying setup, hold, access, retain, cycle time components by adding stress on setup and hold separately and checking for glitches, pushout/pullin, pulse width violations. Understanding of circuits: Negative Bitline for write assist and Read assist.

Custom memory Design. Worked on memories like L1 cache, L2 cache, ROM memories. Exposure to circuits like Keeper, Write Wordline Boost for write assist, Sense amplifier. Optimizing performance in different technology nodes like, TSMC 16nm, 7nm, 5nm, GF 14nm and 12nm. Worked on closing timing using Nanotime and cross checking with hspice. Bitmapping memory for post Silicon validation. Pluging ROM memories for final Silicon. Logical verification of memory using espcv and lec tools.