Alejandro Martin

Research and development of the modem for a LRDL (Long Range Data Link) System based on Picozed-SDR (Software Define Radio) which integrates a Xilinx FPGA Zynq 7035i and an Analog Devices AD9361 RF Front-End in the microwave C-Band (5Ghz). Development of SOTM (Satellite On The Move) in the Ku-Band (11-12 GHz) for LEO satellite connectivity and tracking. Based on the Xilinx RF-SoC. Tools: Xilinx Vivado 2019.2 and 2020.2 System Generator Vivado HLS (C/C++) Matlab 2019b and 2020b Petalinux 2019.2

Development and verification of an interface adapter for the BRIMSTON and SPEARS 3 families of MBDA Missiles to be compatible with the fighter planes Eurofighter and Lookheed-Martin F35 using the MIL-BUS 1553 interface. Development in VHDL and verification using regression tests in Questa Sim in VHDL and SystemVerilog for Verification (UVM). Environment: Mentor Questa Sim 10.7, Sigasi, IBM Rational DOORS

FPGA development of a control unit for a 3D Crashtest system based on one Xilinx Zynq 7045 and eight analog front-end systems, each controlled with one with a Xilinx Artix 7 and diverse ADC and DAC. Implementation of control units for LVDT and SSI sensors, communication interfaces between diverse boards and FPGAS as well as sensors (I2C, SPI, USB, FSB, UART, Ethernet Gbit). Design was developed in VHDL under Vivado 2018.2, Sigasi Studio 4.3 and Modelsim Mentor Graphics 10.7.

Nachrichtentechnik, FPGA, Mikroelektronik, VHDL, Signalverarbeitung, Digital- und Anlagenentwicklung, Funksysteme, Mikrowellensysteme, Computersysteme, IT usw