Amr Hegazy

Worked with the Digital Verification Technologies QA Team (DVT QA). Our Project dealt with the FPGA Synthesis Process and incorporating innovative ML solutions to increase efficiency, ease of use and evolve the EDA & FPGA Synthesis Workflow. We aimed to predict synthesis features that concern specific hardware resources like RAMs, DSPs & FSMs instead of relying on the traditional synthesis process.

• Development of floorplanning self-identification ML-platform that includes: • Image processing to identify key features in floorplans and generate a simplified yet standardized version of it. • Trained Machine Learning models to identify door, windows, zones,...etc. • Generate labeled AutoCAD format for 3D modeling stage. • Constructed floorplan 3D models.

Thesis Topic: Safety Guaranteed Utilization of Foundation Large Language Models in Robotics Using Reachability Analysis