Ing. Aneesh Pindalavalappil Sathyan

•Operate Berkeley Advanced Reconstruction Toolbox on VCK190 within PetaLinux OS. •Offload parts of BART arithametic operations to PL or AI engine to reduce CPU overhead.

•Increased data transmission rate from 25 MHz to 100 MHz using the CMAC IP core. •Added payload checksum calculation in both ingress and egress paths. •Enabled control-plane updates via PCIe for dynamic configuration.

•Tested on CMAC, 10G/25G Ethernet, and Corundum IP cores (Oscilloscope readings). •Achieved improved timing accuracy and data consistency.

Designed a triggerless DAQ system on the ZC706 SoC. •Developed a Vivado RTL architecture achieving 100% noise filtration. •Increased throughput from 2 GB/s to 6.4 GB/s using buffered DAQ, MIG-7, and DDR3. •Performed HDL simulation, synthesis, hardware implementation, and bare metal testing using Vitis. •Integrated PCIe for efficient host-to-card communication.

Coursework focused on FPGA and SoC design using VHDL, SystemVerilog, and High-Level Synthesis, with emphasis on RTL development and AXI/AMBA-based integration. Included ASIC design flow (synthesis, place-and-route, and timing analysis) and hands-on experience with Vivado, Vitis, HLS, and UVM tools. Also covered embedded systems programming in C/C++, scripting in Python, P4, TCL, and Bash, and communication protocols like Ethernet, PCIe, UART, I2C, Profinet, and Profibus.

Focused on analog and digital circuit design, embedded systems, embedded programming, microprocessors, and microcontrollers, building a strong foundation in both hardware design and system-level programming.