Ing. Aneesh Pindalavalappil Sathyan

Orchestrated FPGA components for seamless data transfer and noise detection in Open Interface Computed Thermography on ZC706 SoC. • Designed Vivado RTL integrating Zynq PS and AXI DMAs for detector data transfer. • Implemented packet header separation, timestamp-based sorting, and noise removal. • Utilized MIG7 DDR3 for efficient storage and processing. • Performed HDL simulation, synthesis, hardware validation, and Vitis C++ testing. • Added PCIe with XDMA for reliable bi-directional data transfer.

Coursework focused on FPGA and SoC design using VHDL, SystemVerilog, and High-Level Synthesis, with emphasis on RTL development and AXI/AMBA-based integration. Included ASIC design flow (synthesis, place-and-route, and timing analysis) and hands-on experience with Vivado, Vitis, HLS, and UVM tools. Also covered embedded systems programming in C/C++, scripting in Python, P4, TCL, and Bash, and communication protocols like Ethernet, PCIe, UART, I2C, Profinet, and Profibus.

Focused on analog and digital circuit design, embedded systems, embedded programming, microprocessors, and microcontrollers, building a strong foundation in both hardware design and system-level programming.