Attila Zsigmond

Angestellt, ASIC Design Engineer, Intel Deutschland GmbH
Munich, Germany

Fähigkeiten und Kenntnisse

RTL Design (not main focus though)
SDC
Digital Synthesis (Synopsys DC)
Simulations (RTL functional & back-annotated netli
Floorplanning
Placement
Routing
Extraction and STA
Formal Verification
Customer Support
TCL / Perl
Digital Design Implementation (RTL to GDS)
Innovus
tempus
quantus
PNR
STA

Werdegang

Berufserfahrung von Attila Zsigmond

  • Current 4 years and 8 months, since Nov 2021

    ASIC Design Engineer

    Intel Deutschland GmbH
  • 3 years and 1 month, Oct 2018 - Oct 2021

    Lead Application Engineer

    Cadence Design Systems, Inc.

  • 1 year and 5 months, May 2017 - Sep 2018

    ASIC Development Engineer

    ZF Group

    Providing technical expertise and project management services for the “Sensors Team” for a mixed signal ASIC project developed in partnership with a third-party provider. Main technical interface between ZF-TRW Team and ASIC provider.

  • 6 months, Oct 2016 - Mar 2017

    Synthesis and FV Engineer - Contractor

    Renesas Electronics Europe GmbH

    - Digital Synthesis with Cadance RC on advanced process nodes (16 nm) - Formal Verification LEC / Formality - SDC analysis with Synopsys GCA - Flow optimization

  • 4 years and 2 months, Aug 2012 - Sep 2016

    Digital Design Engineer / Customer Application Engineer

    eASIC Corp.

    - Implementation of digital design on eASIC's proprietary structured ASICs (28nm and 45nm), from RTL to GDSII, thus having a comprehensive understanding of all digital design steps - Responsible for technical customer support during whole project life cycle, often offering on-site support

  • 9 months, Nov 2011 - Jul 2012

    Intern

    eASIC Corp.

  • 3 months, Sep 2011 - Nov 2011

    Rework Technician

    Benchmark Electronics

    PCB level debug on high complexity products.

Ausbildung von Attila Zsigmond

  • 1 year and 10 months, Oct 2011 - Jul 2013

    Telecommunication and Electrical Engineering

    "Transilvania" University of Brasov

  • 3 years and 10 months, Oct 2007 - Jul 2011

    Telecommunications and Electrical Engineering

    "Transilvania" University of Brasov

Sprachen

  • Hungarian

    C2 (Verhandlungssicher / Muttersprachlich)

  • Romanian

    C2 (Verhandlungssicher / Muttersprachlich)

  • English

    C1 (Fließend)

  • German

    A1-A2 (Grundkenntnisse)

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