Bhavik Markana

Implement modes as per the IPXACT 2021 standard and changes in the memory map and interfaces. UVM TB flow implementation - uses VIP and VCS sequences to generate register compliance report. Gain knowledge about leveraging standard interfaces for Subsystem auto-connection and net-listing. Develop a proc to generate proper include paths for VCS and formality to point include files correctly. Implement methodology/flows to support Synthesis (DC), primetime (STA), formality and ATPG.

IP Processing, Qualification and Generation of various views required for full chip in SOC Integration. Parsing views like Verilog, SV, LIB and LEF to extract required information like pin & direction etc. Processing physical views like GDS and MW to extract required information for IP qualification. Implemented wrapper script for regression suite useful in IP processing, qualification and Tool release.

Develop automation to program BIST algorithms for validating memories in graphics and display units. Test case development for validation of algorithms related to MEMDFT. RTL Design of re-configurable adder using Verilog and Verification using directed testbench flow. Perl automation to generate directed testbenches and to run the simulation and verify the results. Golden models for verifying results with RTL simulation for adder.

Courses: Digital Circuit and Logic Design, Advanced Embedded System, Advanced Microcontrollers, Advanced Engineering Mathematics, VLSI Design and Verification, Coding Theory, Digital System Design using Verilog.

Digital Circuit and Logic Design, Embedded System, Microprocessor , Operating System Engineering Mathematics, VLSI Design , Error Coding Theory, Control System, OOPs, C , C++