Akib Mohamamad Azam Zaidi

Development of Testbench in SystemVerilog -UVM Development of Testcase for Functional Verification Development of Coverage Metric for Functional Verification Development of Assertions in SystemVerilog Assertions (SVA)

Analog circuit design Digital IC design using SystemVerilog/Verilog implementation. Development of Reusable designs. Functional and Formal pre-silicon verification, using SV-Assertions. Function Verification of block-level Modules using verilog. Python-based automation and optimization Skill-based scripting automation

Front-End Verification of different ASIC designs Developing behavioral analog models for schematics in Verilog-AMS Develop assertion/fault mechanism for electrical and digital inputs Self-checking Testbench development using different Hardware Verification Languages to validate analog schematics and models in Verilog, Verilog-AMS and SystemVerilog Debug any design issue or plan a solution to fix the issue Running top level simulation using both analog models and RTL Developing scripts in Python/Bash