Boris Kamewe Tametang

Design of an ultra low Power autonomous CMOS Sensor, into a 65 nm Process. -Circuitry sizing, Transcient and Temperature Analysis on SPECTRE environment. -Professional Layout design : -Transistors Matching. -Design Rules Check on CALIBRE environment (DRC Analysis). -Layout Versus Schematic Check (LVS). -Parasites Extraction and Post-Layout View (QRC).

Development on Android of a software for a Universal Bluetooth to Infrared remote control based on a DE2 115 board (FPGA). a)Bluetooth/IR frames conversion. b) IR frames transmission with NEC and RC5 protocols. c) Development of a Software interface by mapping on Android.

Softkinetic Belgium : Characterization of new CMOS Sensors Structures for the measurement of the Time Of Flight a)Classification of Avalanche Photodiode Diodes (APD) structures, thanks to their pitch and to the Bulk Voltage. b) DC Analysis : Measurement of the responsivity. c) AC Analysis : Measurement of the structures strength and the Cut-off frequency.

Design of An Ultra Low-Voltage, Ultra Low-Power CMOS Miller OTA with Rail-to-Rail Input/Output Swing into a 150nm process. a) Circuitry sizing, Transcient and Temperature Analysis on SPECTRE environment. b) Measurement of Bandpass, Phase Margin and Gain of the Amplifier. c) Professional Layout design : d) Transistors Matching. e) Design Rules Check on CADENCE environment (DRC Analysis). f) Layout Versus Schematic Check (LVS). g) Parasites Extraction and Post-Layout View (QRC).

Advanced Teachers Training Education School, Douala-Cameroun.

Design of an ultra low Power autonomous CMOS Sensor, into a 65 nm Process. a)Circuitry sizing, Transcient and Temperature Analysis on SPECTRE environment. b)Professional Layout design : c)Transistors Matching. d)Design Rules Check on CALIBRE environment (DRC Analysis). e)Layout Versus Schematic Check (LVS). f)Parasites Extraction and Post-Layout View (QRC).

Power electronics/Leistungselektronik, Renewable energy/Erneuerbaren Energien, Electrical machines/Elektrische Maschinen

Design of An Ultra Low- Power CMOS Temperature Sensor for ZIGBEE applications, into a 150 nm process. a)Temperature Analysis of the PTAT (Proportional To Absolute Temperature). b) Professional Layout design in accordance with IDESA Tutorials.

Advanced Teachers Training Education School, Douala-Cameroun.