Chia-Yu Hsieh

Responsible for front-end analog circuit of a cooperative project with biological research - Front-end circuit design (EM simulation, circuit design, on-wafer probing) - 2.4 GHz PLL design - Wake-up receiver design (LNA) - Class-E power amplifier design - Interface between MCU and analog circuit (VHDL coding and synthesis)

Bluetooth System design and Verification - EVB design for test benches and customer products - RF performance verification, tuning and debug - Co-work with RF/digital designers and algorithm/SW engineers to verify the design and find out the issue roos causes - Customer support and issue debug - Coexistence verification with WIFI/GSM - RF Output impedance matching (chip to antenna) - Design document transfers to overseas branches

RF Circuit Design and Measurement - 60 GHz front-end component circuit design/ on-wafer measurement - 60 GHz buffer amplifier design - 60 GHz variable gain amplifier design