Daniel Rivas

As System and Platform Architect I was involved in Path Finding activities for the new SDI Rack Scale architectures and Omni-Path Interconnect to help define future platforms. Worked also as HPC Software Engineer doing performance modeling and performance projection for scale-up and scale-out systems.

- Performance modeling. Main developer of a performance simulator for fast simulation of the entire memory hierarchy, including caching agents and cache coherency protocols, matching the architecture of a follow-on 10nm Intel® Xeon Phi™ product. - Silicon Architect. Working on the uncore team doing performance evaluations of the coherent subsystem of a follow-on 10nm Intel® Xeon Phi™ product helping defining the architecture of the mesh interconnect, new memory coherency protocols and cache sizes.