Emre Ayranci

Organize professional activities and coordinate IEEE GOLD (Graduates of Last Decade) members of Benelux Section, hold workshops and represent Benelux section in IEEE congresses.

Design of blocks in the receiver and the transceiver of Gigabit and 10 Gigabit Ethernet in 65nm & 40nm processes

10Gb/s+ networking products. Design, test, layout and simulation of PLLs, CDRs and EDC, SiGe BiCMOS & CMOS processes, in-company trainings "45% power saving in a 0.25μm BiCMOS 10Gb/s 50Ω-terminated packaged active-load laser driver" has been presented and published in ISSCC 07. Project "Enhancement of phase noise performance and linearization of VCOs by Frequency Locked Loop and implementation in a PLL" was realised including Phase/voltage domain Verilog-A modeling & transistor level design. Finalist (top

Analog & RF IC design

analog ic design