Faten Lariani

-Partitioning of designs on multi-FPGAs targets. -Optimizing the partitioning process. -Technologies: FPGA, Multi-FPGA, Hypergraph, C++.

* Development of an FPGA IP Verilog Generator and Integrating it into an MPSoC Architecture as a configurable accelerator (Master Thesis and End of studies project) - Design and implement a Verilog generator of a new FPGA architecture. - The generator uses a compact and performant Mentor Graphics proprietary data-structure that creates FPGA’s netlist in Verilog. - Implement the generator using C++ and optimizing the FPGA interconnect generator implementation.

Acoustic Model Generator : -Design and development of an acoustic model that identifies keywords in C++. - Detect and identify keywords from a continuous audio data flow buffer in order to launch some set of actions automatically in real-time. - Technologies: C/C++, kernel linux, signal processing, FFT.

*Detection of overlapping communities in bipartite graphs using Spark Streaming, - Design and development of a new distributed solution that identifies overlapping communities in bipartie graphs. - Deployment of the solution on a cluster to test the parallelism of the algorithm. - Technologies: Spark, SparkStreaming, MapReduce, HDFS, Scala, Maven, Eclipse

* Design and Realization of a Mobile Application ’Electronic Visit Card’ - Multithreaded solution of text recognition for Visit Cards. - Developpment of an android application. - Manipulation of textual recognition algorithms - Technologies: Spark, SparkStreaming, MapReduce, HDFS, Scala, Maven, Eclipse

Diploma obtained with honors VERY GOOD and MAJOR OF PROMOTION