Guido Schlothane

Engineering Manager of multi-national team of 10+ highly skilled Physical Design engineers • responsible for service provision in leading edge technology based low power RF telecommunication consumer applications • resource planning, people development and timeline management in coordination with project management

Intel Business Group representative in IEEE 1801 standardization committee ('UPF')

Responsible for Coordination and Roadmap of Low Power Implementation and Verification Methodology in <28nm semiconductor mobile communication applications. Driver for UPF standard to tool development at major EDA vendors Resource planning, methodology project coordination and execution with interface to internal project development teams

project lead for low power methodology projects in <65nm semiconductor development for mobile com applications.

Team member design methodology innovation projects (Timing Reference Engine) Project management silicon test-chip development in 110 and 90nm technlogies Author of RTL2GDS Handover section in company silicon development handbook SDHB

Responsible for Physical Design (Logic Synthesis) Responsible for Static Timing Analysis (STA) Responsible for Design For Test (including industry first application of embedded Scan Chain Compressor) Data Configuration Management and Storage Coordination

Hardware Development of <90nm semiconductor development for mobile com applications (wire-line). RTL development in VHDL and Validation, Logic Synthesis and Static Timing Analysis

Mikroelektronik / Informationstechnik